Patents by Inventor Hiroki Shimano
Hiroki Shimano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7626883Abstract: During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner.Type: GrantFiled: May 5, 2008Date of Patent: December 1, 2009Assignee: Renesas Technology Corp.Inventors: Hiroki Shimano, Kazutami Arimoto
-
Publication number: 20090207642Abstract: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.Type: ApplicationFiled: February 20, 2009Publication date: August 20, 2009Inventors: Hiroki SHIMANO, Kazutami Arimoto
-
Publication number: 20090103353Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: ApplicationFiled: December 18, 2008Publication date: April 23, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Patent number: 7480168Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: GrantFiled: June 28, 2007Date of Patent: January 20, 2009Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Publication number: 20080279017Abstract: During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner.Type: ApplicationFiled: May 5, 2008Publication date: November 13, 2008Inventors: Hiroki Shimano, Kazutami Arimoto
-
Publication number: 20080175038Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: ApplicationFiled: June 28, 2007Publication date: July 24, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Publication number: 20080137394Abstract: One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.Type: ApplicationFiled: December 12, 2007Publication date: June 12, 2008Inventors: Hiroki Shimano, Fukashi Morishita, Kazutami Arimoto
-
Patent number: 7248495Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: GrantFiled: April 5, 2006Date of Patent: July 24, 2007Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Patent number: 7139208Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.Type: GrantFiled: June 24, 2005Date of Patent: November 21, 2006Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume
-
Publication number: 20060193164Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: ApplicationFiled: April 5, 2006Publication date: August 31, 2006Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Patent number: 7046543Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: GrantFiled: August 23, 2004Date of Patent: May 16, 2006Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Publication number: 20060013030Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.Type: ApplicationFiled: June 24, 2005Publication date: January 19, 2006Applicant: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume
-
Patent number: 6980454Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.Type: GrantFiled: September 27, 2004Date of Patent: December 27, 2005Assignee: Renesas Technology Corp.Inventors: Takeshi Fujino, Kazutami Arimoto, Hiroki Shimano
-
Patent number: 6925022Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.Type: GrantFiled: August 28, 2002Date of Patent: August 2, 2005Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume
-
Patent number: 6909658Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.Type: GrantFiled: May 11, 2004Date of Patent: June 21, 2005Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Patent number: 6898137Abstract: In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row activation is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charge in equal amounts is injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.Type: GrantFiled: April 1, 2003Date of Patent: May 24, 2005Assignee: Renesas Technology Corp.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Publication number: 20050041514Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.Type: ApplicationFiled: September 27, 2004Publication date: February 24, 2005Applicant: Renesas Technology Corp.Inventors: Takeshi Fujino, Kazutami Arimoto, Hiroki Shimano
-
Publication number: 20050018471Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.Type: ApplicationFiled: August 23, 2004Publication date: January 27, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutami Arimoto, Hiroki Shimano
-
Publication number: 20050009269Abstract: An isolation film is formed in a surface of a substrate 1 in which active regions are formed, to separate the active regions from each other. Subsequently, a portion of the isolation film is removed, to form a recess, which is then filled with a portion of an upper electrode. Also, an insulating film 8 is interposed between the upper electrode and the substrate.Type: ApplicationFiled: May 21, 2004Publication date: January 13, 2005Inventors: Hiroki Shinkawata, Atsushi Hachisuka, Hiroki Shimano
-
Patent number: 6812532Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.Type: GrantFiled: July 30, 2002Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Tsukasa Ooishi, Hiroki Shimano, Shigeki Tomishima