Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

Abstract: A data storage unit of a ternary content addressable memory (TCAM) cell is constructed by two twin cells each having DRAM cells of two bits, and complementary data are stored in each of the twin cells. One of storage nodes is selected from each of the twin cells. A comparing circuit compares complementary search data on a search data line pair with the selected stored data. In a DRAM cell, a planar metal-insulator-semiconductor (MIS) transistor is used. According to such configuration, the chip area and cost of a ternary content addressable memory are reduced and high-speed writing is achieved.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied to a bit line isolation gate connecting the bit line and the sense amplifier is restricted, and the word line is driven according to a negative voltage non-boosted word line scheme. A well region where a memory block is formed and a well region where the isolation gate is formed are separately provided, and separate bias voltages are applied thereto. Thus, a DRAM (dynamic random access memory)-based logic merged memory is implemented without degrading dielectric breakdown characteristics of the gate insulating film.

Abstract: A data storage unit of a ternary content addressable memory (TCAM) cell is constructed by two twin cells each having DRAM cells of two bits, and complementary data are stored in each of the twin cells. One of storage nodes is selected from each of the twin cells. A comparing circuit compares complementary search data on a search data line pair with the selected stored data. In a DRAM cell, a planar metal-insulator-semiconductor (MIS) transistor is used. According to such configuration, the chip area and cost of a ternary content addressable memory are reduced and high-speed writing is achieved.

Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

Abstract: In a Vss precharge scheme, a dummy cell including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line is arranged in complementary bit lines respectively. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row active is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charges of the same amount are injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.

Abstract: In a memory sub-block, a refresh activation instruction signal from a main control circuit is taken in by a de-multiplexer in a local control circuit under a predetermined condition and refreshing is executed in the memory sub-block. The de-multiplexer is inhibited from taking in this refresh activation instruction signal when an adjacent memory sub-block is in an inactivated state with the corresponding memory block being in an activated state or when refreshing is completed in the corresponding memory sub-block, and transfers this refresh activation instruction signal to a local control circuit arranged for the memory sub-block on the next stage in a refresh activation instruction signal transferring path. Upon completion of refreshing in all the memory sub-blocks, refreshing is carried out on the next refresh address. It is possible to provide a semiconductor memory device which can fully hide a refreshing operation from outside.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.

Abstract: Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied to a bit line isolation gate connecting the bit line and the sense amplifier is restricted, and the word line is driven according to a negative voltage non-boosted word line scheme. A well region where a memory block is formed and a well region where the isolation gate is formed are separately provided, and separate bias voltages are applied thereto. Thus, a DRAM (dynamic random access memory)-based logic merged memory is implemented without degrading dielectric breakdown characteristics of the gate insulating film.

Abstract: In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.

Abstract: A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Abstract: A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For each redundant replacement unit, a program element is arranged for stopping supply of a cell plate voltage from the cell plate voltage line to the cell plate electrode line. The program element corresponding to the cell plate electrode line short-circuited to the word line nonvolatilely changes from the on state to the off state in response to an externally supplied input instruction.

Abstract: In a memory sub-block, a refresh activation instruction signal from a main control circuit is taken in by a de-multiplexer in a local control circuit under a predetermined condition and refreshing is executed in the memory sub-block. The de-multiplexer is inhibited from taking in this refresh activation instruction signal when an adjacent memory sub-block is in an inactivated state with the corresponding memory block being in an activated state or when refreshing is completed in the corresponding memory sub-block, and transfers this refresh activation instruction signal to a local control circuit arranged for the memory sub-block on the next stage in a refresh activation instruction signal transferring path. Upon completion of refreshing in all the memory sub-blocks, refreshing is carried out on the next refresh address. It is possible to provide a semiconductor memory device which can fully hide a refreshing operation from outside.

Abstract: An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrode is connected to the interconnection layer. The interconnection layer supplies a high voltage for breaking a dielectric of a program element. A voltage on a P-type well is externally adjusted via a resistance element. Thereby, erroneous program due to serge entering at the interconnection layer can be avoided.

Abstract: When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.