Abstract: A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.

Abstract: A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.

Abstract: A plurality of test interface circuits are disposed in correspondence with a plurality of DRAM cores. An upper test interface circuit transmits a test control signal or the like supplied from the outside to each of or one of the plurality of test interface circuits in accordance with a memory core selection signal. When all of the DRAM cores are designated as targets of an operation test, test output data from the DRAM cores is compared with each other by a data comparing circuit and is outputted as judge flag data reflecting the result of the comparison to the outside.

Abstract: Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.

Abstract: A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.

Abstract: When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.

Abstract: Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.

Abstract: A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

Abstract: There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zo

Abstract: A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.

Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.

Abstract: A redundant memory cell column region provided corresponding to respective regular memory cell column regions can have data read and written through a sub I/O line pair and a main I/O line pair independent to those of the regular memory cell column region. Also, one redundant memory cell column region can be connected to a corresponding global I/O line pair G-I/O of any of the regular memory cell column regions via a multiplexer to be replaceable of any of two regular memory cell column regions.

Abstract: A sub word line is selected when an associated word line and any of sub decode lines are driven to attain a boosted potential. In a sub decoder selectively driving any of the sub decode lines, the pull-down transistors allowing the sub decode line to discharge are turned on successively with time in a pulsing manner.

Abstract: A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.

Abstract: In a word line drive circuit for driving a word line to a boosted voltage level, a drive signal that is activated in response to a wafer burn-in signal is applied to the gate of a transistor for preventing the floating state of the word line. Even if a boost signal is transmitted to a corresponding word line through a word line driver circuit, the floating state prevention transistor can be turned off at high speed, an electric charge flow path can be cut off, and the word line can be driven reliably to the boosted voltage level. Therefore, reliable burn-in can be implemented.

Abstract: A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test clock signals, and the memory circuit is provided with a signal/data according to the other test clock signal. Thus, the set-up time and the hold time of a signal for the memory can be measured with accuracy in a memory-merged system LSI.

Abstract: In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.

Abstract: A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is electrically connected to cell plate and dummy bit line. Thus, a semiconductor memory device is obtained in which a cell plate voltage can reliably be fed to a cell plate while preventing the increase of the area of a chip.