Abstract: In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.

Abstract: A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For each redundant replacement unit, a program element is arranged for stopping supply of a cell plate voltage from the cell plate voltage line to the cell plate electrode line. The program element corresponding to the cell plate electrode line short-circuited to the word line nonvolatilely changes from the on state to the off state in response to an externally supplied input instruction.

Abstract: There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zo

Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

Abstract: There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.

Abstract: A plurality of test interface circuits are disposed in correspondence with a plurality of DRAM cores. An upper test interface circuit transmits a test control signal or the like supplied from the outside to each of or one of the plurality of test interface circuits in accordance with a memory core selection signal. When all of the DRAM cores are designated as targets of an operation test, test output data from the DRAM cores is compared with each other by a data comparing circuit and is outputted as judge flag data reflecting the result of the comparison to the outside.

Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.

Abstract: When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.

Abstract: A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

Abstract: There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zo

Abstract: A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test clock signals, and the memory circuit is provided with a signal/data according to the other test clock signal. Thus, the set-up time and the hold time of a signal for the memory can be measured with accuracy in a memory-merged system LSI.

Abstract: A sense operation by a sense amplifier circuit is carried out by selecting a pair of subword lines simultaneously and coupling each bit line in a pair to a memory cell. Since complementary data are stored into these two memory cells, the voltage between the bit lines in a pair in a sense operation can be set large enough to allow increase of the refresh interval. Therefore, power consumption in a data retaining mode can be reduced.

Abstract: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

Abstract: A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.

Abstract: In a word line drive circuit for driving a word line to a boosted voltage level, a drive signal that is activated in response to a wafer burn-in signal is applied to the gate of a transistor for preventing the floating state of the word line. Even if a boost signal is transmitted to a corresponding word line through a word line driver circuit, the floating state prevention transistor can be turned off at high speed, an electric charge flow path can be cut off, and the word line can be driven reliably to the boosted voltage level. Therefore, reliable burn-in can be implemented.

Abstract: An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrode is connected to the interconnection layer. The interconnection layer supplies a high voltage for breaking a dielectric of a program element. A voltage on a P-type well is externally adjusted via a resistance element. Thereby, erroneous program due to serge entering at the interconnection layer can be avoided.

Abstract: In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.

Abstract: A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is electrically connected to cell plate and dummy bit line. Thus, a semiconductor memory device is obtained in which a cell plate voltage can reliably be fed to a cell plate while preventing the increase of the area of a chip.