Patents by Inventor Hiroki Yamashita

Hiroki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160079252
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor pillar extending in a first direction, a first insulating film, a second insulating film, a third insulating film, a first portion of a first electrode provided to be in contact with an outer surface of the first insulating film, a second portion of the first electrode provided to be in contact with an outer surface of the first insulating film, a third portion of the first electrode provided to be in contact with the first insulating film, a forth insulating film provided on an outer surface of the first electrode, and a second electrode provided on an outer surface of the forth insulating film. An outer diameter of the first portion is larger than an outer diameter of the third portion.
    Type: Application
    Filed: July 10, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroki YAMASHITA
  • Publication number: 20160013200
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
    Type: Application
    Filed: September 11, 2014
    Publication date: January 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroki YAMASHITA
  • Publication number: 20150255500
    Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: TOSHITAKA AKAHOSHI, HIROKI YAMASHITA, SHIGEFUMI DOHI
  • Patent number: 9123823
    Abstract: According to embodiment, a nonvolatile semiconductor memory device, includes: a memory cell region; and a peripheral region, the memory cell region including: a semiconductor layer including semiconductor regions; control gate electrodes; a first insulating film; a semiconductor-containing layer having a smaller thickness than the first insulating film; and a second insulating film, the peripheral region including: the semiconductor layer; a third insulating film; the semiconductor-containing layer, and a periphery of the semiconductor-containing layer being surrounded by an element isolation region; the first insulating film provided on the semiconductor-containing layer; and a pair of conductive layers extending from a surface of the first insulating film to reach the third insulating film via the semiconductor-containing layer, and the pair of conductive layers being in contact with part of a lower surface of the semiconductor-containing layer.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: September 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shun Shimizu, Hiroki Yamashita
  • Publication number: 20150222236
    Abstract: The high-speed and high-quality reception operation of a transimpedance amplifier of an optical communication module and a router including the same can be achieved. A preamplifier performs current/voltage conversion with respect to intersymbol interference due to bandwidth shortage of a laser diode. A threshold control circuit which generates positive and negative threshold voltages with respect to a center potential of an output signal, latch circuits, and a selector circuit are provided to the output of the preamplifier. An NRZ signal is received as a duobinary signal based on the sign determination result of the previous bit. The determination error rate of the latch circuits can thus be improved.
    Type: Application
    Filed: January 17, 2015
    Publication date: August 6, 2015
    Inventors: Takashi Takemoto, Hiroki Yamashita
  • Patent number: 9059303
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body having a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film, a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 16, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Aoyama, Tatsuya Okamoto, Hiroki Yamashita, Masanari Hattori
  • Patent number: 9054655
    Abstract: Provided is a transimpedance amplifier which can realize a high-speed and high-quality receiver operation in an optical communication module or a router device having the optical communication module. An offset voltage which is generated in a post amplifier for differentiating and amplifying a single-phase output signal from a pre-amplifier in accordance with single-phase differentiation and conversion is cancelled by detecting a threshold voltage from an output of the pre-amplifier or an output of the post amplifier by a threshold detection circuit and by shifting a level of the threshold voltage corresponding to an offset amount to be compensated.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: June 9, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita
  • Patent number: 8993952
    Abstract: An optical module including a transimpedance amplifier capable of realizing a high-speed and high-quality receiving operation is provided. A transimpedance amplifier includes: a pre-amplifier using a single-end current signal as an input and converting the single-end current signal to a single-end voltage signal; an automatic decision threshold control detecting a center electric potential of the single-end voltage signal serving as an output of the pre-amplifier; a post-amplifier differentiating and amplifying the single-end voltage signal of the output of the pre-amplifier; and a power circuit supplying power to the pre-amplifier. Particularly, in accordance with an input voltage signal or an output voltage signal of the pre-amplifier, the power circuit outputs a varied current that flows to a supply terminal of the pre-amplifier and a varied current having a phase opposite to that of the varied current. Thus, the power supply current change is cancelled out.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 31, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Shinji Tsuji
  • Publication number: 20150069495
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body having a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film, a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.
    Type: Application
    Filed: January 24, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji AOYAMA, Tatsuya OKAMOTO, Hiroki YAMASHITA, Masanari HATTORI
  • Publication number: 20150060984
    Abstract: According to embodiment, a nonvolatile semiconductor memory device, includes: a memory cell region; and a peripheral region, the memory cell region including: a semiconductor layer including semiconductor regions; control gate electrodes; a first insulating film; a semiconductor-containing layer having a smaller thickness than the first insulating film; and a second insulating film, the peripheral region including: the semiconductor layer; a third insulating film; the semiconductor-containing layer, and a periphery of the semiconductor-containing layer being surrounded by an element isolation region; the first insulating film provided on the semiconductor-containing layer; and a pair of conductive layers extending from a surface of the first insulating film to reach the third insulating film via the semiconductor-containing layer, and the pair of conductive layers being in contact with part of a lower surface of the semiconductor-containing layer.
    Type: Application
    Filed: January 27, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shun SHIMIZU, Hiroki Yamashita
  • Publication number: 20150017760
    Abstract: According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members.
    Type: Application
    Filed: October 1, 2014
    Publication date: January 15, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Yamashita
  • Patent number: 8871602
    Abstract: According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Yamashita
  • Patent number: 8772880
    Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Publication number: 20140103504
    Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 17, 2014
    Applicant: Panasonic Corporation
    Inventors: HIROKI YAMASHITA, TAKASHI YUI, TAKESHI KAWABATA, KIYOMI HAGIHARA, KENJI YOKOYAMA
  • Patent number: 8674725
    Abstract: A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Kurahashi, Tomofumi Hokari, Takashi Muto, Goichi Ono, Hiroki Yamashita
  • Publication number: 20130342275
    Abstract: Provided is a transimpedance amplifier which can realize a high-speed and high-quality receiver operation in an optical communication module or a router device having the optical communication module. An offset voltage which is generated in a post amplifier for differentiating and amplifying a single-phase output signal from a pre-amplifier in accordance with single-phase differentiation and conversion is cancelled by detecting a threshold voltage from an output of the pre-amplifier or an output of the post amplifier by a threshold detection circuit and by shifting a level of the threshold voltage corresponding to an offset amount to be compensated.
    Type: Application
    Filed: May 23, 2013
    Publication date: December 26, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Takashi TAKEMOTO, Hiroki YAMASHITA
  • Patent number: 8503595
    Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 6, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8503888
    Abstract: An optical communication module and an optical communication device including the same are provided. For example, a first semiconductor chip on which a laser diode is formed and a second semiconductor chip on which a laser diode driver circuit, etc. for subjecting the laser diode to drive by current are formed are mounted on a package printed circuit board to be close to each other. Temperature detecting means is further formed on the second semiconductor chip (laser diode driver circuit, etc.). The temperature detecting means detects a temperature variation ?T of the first semiconductor chip (laser diode) transmitted via a wiring in the package printed circuit board and controls the magnitude of the driving current of the laser diode driver circuit based on a detection result.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 6, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Shinji Tsuji
  • Patent number: 8493103
    Abstract: Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: July 23, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8445832
    Abstract: An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: May 21, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Tatsuya Saito