Patents by Inventor Hiroki Yamashita

Hiroki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130059426
    Abstract: According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members.
    Type: Application
    Filed: March 16, 2012
    Publication date: March 7, 2013
    Inventor: Hiroki YAMASHITA
  • Patent number: 8358708
    Abstract: A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: January 22, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Masayoshi Yagyu
  • Publication number: 20130016748
    Abstract: An optical module including a transimpedance amplifier capable of realizing a high-speed and high-quality receiving operation is provided. A transimpedance amplifier includes: a pre-amplifier using a single-end current signal as an input and converting the single-end current signal to a single-end voltage signal; an automatic decision threshold control detecting a center electric potential of the single-end voltage signal serving as an output of the pre-amplifier; a post-amplifier differentiating and amplifying the single-end voltage signal of the output of the pre-amplifier; and a power circuit supplying power to the pre-amplifier. Particularly, in accordance with an input voltage signal or an output voltage signal of the pre-amplifier, the power circuit outputs a varied current that flows to a supply terminal of the pre-amplifier and a varied current having a phase opposite to that of the varied current. Thus, the power supply current change is cancelled out.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 17, 2013
    Inventors: Takashi TAKEMOTO, Hiroki YAMASHITA, Shinji TSUJI
  • Patent number: 8311157
    Abstract: A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita, Daisuke Hamano
  • Publication number: 20120249217
    Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
    Type: Application
    Filed: October 4, 2010
    Publication date: October 4, 2012
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8253461
    Abstract: There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Yuki, Hiroki Yamashita, Koji Fukuda
  • Publication number: 20120187980
    Abstract: A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 26, 2012
    Inventors: Hiroaki KURAHASHI, Tomofumi Hokari, Takashi Muto, Goichi Ono, Hiroki Yamashita
  • Publication number: 20120133394
    Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C GOOD and C BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.
    Type: Application
    Filed: September 29, 2009
    Publication date: May 31, 2012
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8149973
    Abstract: A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Publication number: 20110316632
    Abstract: An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
    Type: Application
    Filed: March 5, 2009
    Publication date: December 29, 2011
    Applicant: HITACHI, LTD.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Tatsuya Saito
  • Patent number: 8040776
    Abstract: In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 18, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hidehiro Toyoda, Hiroki Yamashita
  • Publication number: 20110249980
    Abstract: An optical communication module and an optical communication device including the same are provided. For example, a first semiconductor chip on which a laser diode is formed and a second semiconductor chip on which a laser diode driver circuit, etc. for subjecting the laser diode to drive by current are formed are mounted on a package printed circuit board to be close to each other. Temperature detecting means is further formed on the second semiconductor chip (laser diode driver circuit, etc.). The temperature detecting means detects a temperature variation ?T of the first semiconductor chip (laser diode) transmitted via a wiring in the package printed circuit board and controls the magnitude of the driving current of the laser diode driver circuit based on a detection result.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 13, 2011
    Inventors: Takashi Takemoto, Hiroki Yamashita, Shinji Tsuji
  • Patent number: 8037543
    Abstract: An image processing apparatus includes an alteration unit and a control unit. The alteration unit alters a first image file stored in a removable storage medium in order to generate a second image file. The control unit controls to store the second image file in the storage medium without deleting the first image file from the storage medium, if the first image file includes authentication data that is used to authenticate whether the first image file has been altered.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: October 11, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoru Wakao, Hiroki Yamashita
  • Patent number: 8005130
    Abstract: A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hidehiro Toyoda, Tatsuya Saito, Hiroki Yamashita, Norio Chujo
  • Publication number: 20110193595
    Abstract: Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively.
    Type: Application
    Filed: January 8, 2011
    Publication date: August 11, 2011
    Inventors: Koji FUKUDA, Hiroki Yamashita
  • Patent number: 7899144
    Abstract: The present invention is to provide a semiconductor integrated circuit device provided with a sufficient margin to variations of input waveforms. For example, the semiconductor integrated circuit device is provided with a clock and data determination circuit receiving an input data signal and a clock signal and outputting a recovered data signal, a first phase comparison signal and a second phase comparison signal and a clock signal generating circuit generating the clock signal with a phase corrected based on the first phase comparison signal and the second phase comparison signal. The clock and data determination circuit latches the input data signal in synchronization with the clock signal using a plurality of thresholds as determination reference and generates two kinds of candidates composed of combination of a recovered data signal and phase comparison signals by processing a latch result.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: March 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Publication number: 20110001588
    Abstract: There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width.
    Type: Application
    Filed: June 29, 2010
    Publication date: January 6, 2011
    Inventors: Fumio YUKI, Hiroki Yamashita, Koji Fukuda
  • Patent number: 7830167
    Abstract: A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: November 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Goichi Ono, Hiroki Yamashita
  • Patent number: 7795944
    Abstract: In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: September 14, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Yagyu, Hiroki Yamashita, Takashi Takemoto
  • Patent number: 7778922
    Abstract: An agent device is connected to a user device for browsing a merchant site, for selling products online and being served up on the Internet, the merchant site, and a server device of a credit-card company. In the case where an instruction of purchasing a product browsed by the user device is output, the instruction is sent to the agent device. The agent device extracts a credit card number of a credit card held by a user having purchased the product, and inquires of the server device of the credit card company whether the product is to be purchased with the credit card. As an inquiry result, in the case where the product can be purchased online with the credit card, the agent device sends an instruction that the user purchases the product online with the credit card.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 17, 2010
    Assignee: Justsystem Corporation
    Inventors: Kazunori Ukigawa, Hiroki Yamashita