Patents by Inventor Hiromasa Noda

Hiromasa Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140104916
    Abstract: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 17, 2014
    Inventors: Hiromasa NODA, Yasuji KOSHIKAWA
  • Patent number: 8659321
    Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: February 25, 2014
    Inventors: Yuko Watanabe, Yoshiro Riho, Hiromasa Noda, Yoji Idei, Kosuke Goto
  • Patent number: 8638625
    Abstract: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: January 28, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Publication number: 20130258742
    Abstract: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 3, 2013
    Inventors: Hiromasa NODA, Yasuji KOSHIKAWA
  • Patent number: 8451677
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: May 28, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • Patent number: 8391085
    Abstract: A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: March 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Jun Suzuki
  • Patent number: 8330487
    Abstract: The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: December 11, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Publication number: 20120307583
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tetsuaki OKAHIRO, Hiromasa NODA, Katsunobu NOGUCHI
  • Patent number: 8278989
    Abstract: A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: October 2, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 8274855
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 25, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • Publication number: 20120213021
    Abstract: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 23, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Publication number: 20120158347
    Abstract: A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 21, 2012
    Inventors: Hiromasa NODA, Toshio Ninomiya
  • Patent number: 8198883
    Abstract: In a semiconductor device manufactured in a semiconductor chip, an internal circuit generates first and second internal circuit control signals which are produced as a delay time measurement start signal and a delay time measurement stop signal, respectively, which are sent to a delay time measurement circuit. The delay time measurement circuit measures a delay time between the start and the stop signals and outputs the delay time.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Hiromasa Noda, Kenji Yoshida
  • Publication number: 20120133399
    Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 31, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yuko WATANABE, Yoshiro RIHO, Hiromasa NODA, Yoji IDEI, Kosuke GOTO
  • Publication number: 20120134439
    Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 31, 2012
    Applicant: Elpida Memory, lnc.
    Inventors: Takenori Sato, Yoji Idei, Hiromasa Noda
  • Publication number: 20120127814
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 24, 2012
    Inventors: Yoshiro RIHO, Hiromasa NODA, Kazuki SAKUMA
  • Patent number: 8184498
    Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: May 22, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 8068375
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: November 29, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • Publication number: 20110273948
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Application
    Filed: June 24, 2011
    Publication date: November 10, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tetsuaki OKAHIRO, Hiromasa NODA, Katsunobu NOGUCHI
  • Publication number: 20110239062
    Abstract: A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Inventor: Hiromasa NODA