Patents by Inventor Hiromasa Noda

Hiromasa Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6424586
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: July 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Publication number: 20020093870
    Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 18, 2002
    Inventors: Hiromasa Noda, Youji Idei, Osamu Nagashima, Tetsuo Ado
  • Patent number: 6414530
    Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 2, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Hitoshi Tanaka, Hideyuki Aoki
  • Patent number: 6396761
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: May 28, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Publication number: 20020060944
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Application
    Filed: January 9, 2002
    Publication date: May 23, 2002
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Publication number: 20020057619
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an, operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Application
    Filed: January 9, 2002
    Publication date: May 16, 2002
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Publication number: 20020057620
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Application
    Filed: January 9, 2002
    Publication date: May 16, 2002
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Patent number: 6385100
    Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: May 7, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Youji Idei, Osamu Nagashima, Tetsuo Ado
  • Publication number: 20020041531
    Abstract: In a semiconductor integrated circuit device having a first circuit block operating on a power supply voltage supplied through an external terminal and a second circuit block operating on an internal voltage generated by a power supply circuit, a voltage having an absolute value greater than that of the internal voltage is generated by a charge pump circuit; variable impedance means is provided between the output voltage and the internal voltage; and a reference voltage and the internal voltage are compared by a differential amplifier circuit operating on the output voltage generated by the charge pump circuit and the variable impedance means is controlled such that those voltages agree with each other.
    Type: Application
    Filed: December 12, 2001
    Publication date: April 11, 2002
    Inventors: Hitoshi Tanaka, Masakazu Aoki, Shinichiro Kimura, Hiromasa Noda, Tomonori Sekiguchi
  • Publication number: 20020012285
    Abstract: Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.
    Type: Application
    Filed: July 18, 2001
    Publication date: January 31, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Sadayuki Okuma, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi
  • Patent number: 6335893
    Abstract: In a semiconductor integrated circuit device having a first circuit block operating on a power supply voltage supplied through an external terminal and a second circuit block operating on an internal voltage generated by a power supply circuit, a voltage having an absolute value greater than that of the internal voltage is generated by a charge pump circuit; variable impedance means is provided between the output voltage and the internal voltage; and a reference voltage and the internal voltage are compared by a differential amplifier circuit operating on the output voltage generated by the charge pump circuit and the variable impedance means is controlled such that those voltages agree with each other.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: January 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Tanaka, Masakazu Aoki, Shinichiro Kimura, Hiromasa Noda, Tomonori Sekiguchi
  • Publication number: 20010026478
    Abstract: A semiconductor memory device comprising: a memory array including a plurality of word lines and a plurality of bit lines; and a column address decoder for selecting a predetermined bit line from the plurality of bit lines. The column address decoder includes: first and second pre-decoders corresponding to high-order and low-order addresses, respectively; a shift register for using the output signal of the second pre-decoder as an initial value; and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit.
    Type: Application
    Filed: February 22, 2001
    Publication date: October 4, 2001
    Inventors: Hiromasa Noda, Youji Idei, Osamu Nagashima, Tetsuo Ado
  • Publication number: 20010026495
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Application
    Filed: June 7, 2001
    Publication date: October 4, 2001
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Publication number: 20010015666
    Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 23, 2001
    Inventors: Hiromasa Noda, Masakazu Aoki, Hitoshi Tanaka, Hideyuki Aoki
  • Patent number: 6275440
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: August 14, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Patent number: 6240035
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: May 29, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Patent number: 6222406
    Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. In the lattice-like delay circuit, input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: April 24, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Hitoshi Tanaka, Hideyuki Aoki
  • Publication number: 20010000133
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Application
    Filed: December 5, 2000
    Publication date: April 5, 2001
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Patent number: 6128248
    Abstract: A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock signal and outputs a first internal clock signal delayed from the external clock signal. A second input circuit receives the first internal clock signal and outputs a second internal clock signal delayed from the first internal clock signal. The memory device also includes a circuit which counts a clock signal having a frequency higher than that of the external clock signal and a circuit which starts the counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: October 3, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Youji Idei, Masakazu Aoki, Hiromasa Noda
  • Patent number: 5970001
    Abstract: An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: October 19, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Kenji Nishimoto, Yoshitaka Kinoshita, Masakazu Aoki