Patents by Inventor Hironori Tanaka

Hironori Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100200285
    Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.
    Type: Application
    Filed: April 20, 2010
    Publication date: August 12, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Takashi KARIYA, Hironori Tanaka
  • Publication number: 20100181285
    Abstract: A method of manufacturing a capacitor device includes forming at least one through-hole in a capacitor laminate formed with laminated multiple capacitors, conducting a dry desmear treatment in the at least one through-hole after forming the at least one through-hole, and forming seed metal through dry processing in the at least one through-hole after conducting the dry desmear treatment.
    Type: Application
    Filed: September 22, 2009
    Publication date: July 22, 2010
    Applicant: IBIDEN, CO., LTD.
    Inventor: Hironori Tanaka
  • Publication number: 20100155129
    Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 ?m or less.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 24, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro KAWAMURA, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 7714233
    Abstract: A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. The ratio (H/D) of a height H of the solder bumps from solder resist layer surface to an opening diameter of the openings are made to be about 0.55 to about 1.0 with the pitch of the openings provided in the solder resist layer of about 200 ?m or less.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 11, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Publication number: 20100065323
    Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Application
    Filed: November 19, 2009
    Publication date: March 18, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Publication number: 20100064512
    Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.
    Type: Application
    Filed: October 29, 2009
    Publication date: March 18, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Takashi KARIYA, Hironori Tanaka
  • Publication number: 20100043942
    Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Application
    Filed: November 9, 2009
    Publication date: February 25, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Patent number: 7649748
    Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: January 19, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Hironori Tanaka
  • Patent number: 7628329
    Abstract: An image processing device includes a judgement section and a generation section. A latent image, which would be retained or eliminated by photocopying, is to be superposed with machine-readable code images, which are encoded supplementary information, to generate a superposed image. The judgement section judges overlapping of the latent image with the machine-readable code images. The generation section, on the basis of judgement results from the judgement section, determines an arrangement of the machine-readable code images and generates the superposed image.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: December 8, 2009
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Hironori Tanaka, Takahiro Saito, Yukio Iijima, Hideo Fujii, Hajime Ichida, Yuka Aoki, Junichi Matsunoshita, Takeshi Onishi
  • Publication number: 20090293271
    Abstract: A printed wiring board is manufactured by a method in which an alignment mark is formed in a metal foil, a bump is formed on the metal foil at a position determined based on the alignment mark, an electronic component is aligned with the bump based on the alignment mark, the electronic component is connected with the bump, and an insulation layer is formed over the electronic component.
    Type: Application
    Filed: May 21, 2009
    Publication date: December 3, 2009
    Applicant: IBIDEN CO., LTD.
    Inventor: Hironori Tanaka
  • Patent number: 7624610
    Abstract: Laser beam irradiation areas are provided in a load curve portion and an angle adjustment portion of a suspension. The laser beam irradiation areas are oriented in a direction in which the suspension is to be bent. A laser beam having a predetermined length and a predetermined shape is irradiated onto each laser beam irradiation area.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: December 1, 2009
    Assignee: NHK Spring Co., Ltd.
    Inventors: Masaru Inoue, Hiroshi Kawamata, Hironori Tanaka
  • Patent number: 7605584
    Abstract: There is provided a voltage generating apparatus that outputs a power source voltage from a voltage outputting terminal.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: October 20, 2009
    Assignee: Advantest Corporation
    Inventors: Hiroki Andoh, Hironori Tanaka
  • Publication number: 20090244865
    Abstract: A method for manufacturing a multilayer printed wiring board having an electronic component housed therein includes forming a first conductor circuit on a first surface of a substrate. A first alignment mark is formed on the first surface of the substrate separate from the conductor circuit and forming a through bore in the substrate, the through bore extending from the first surface of the substrate to a second surface of the substrate. A seal member is disposed on the second surface of the substrate, the seal member sealing an opening on the second surface of the through bore to provide a sealed through bore. An electronic component is inserted in the sealed through bore using the first alignment mark on the first surface of the substrate.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: IBIDEN CO., LTD
    Inventor: Hironori TANAKA
  • Publication number: 20090242252
    Abstract: A multilayer printed wiring board and method for manufacturing a multilayer printed wiring board. One method include a method for manufacturing a multilayer printed wiring board having an electronic component housed therein. The method includes forming a conduction circuit on a core substrate and forming an alignment mark on the core substrate separate from the conduction circuit. Also included is forming a concavity in the core substrate, the concavity being formed in an area of the core substrate not including the conductor circuit and alignment mark, and inserting the electronic component into the concavity in the core substrate by using the alignment mark on the core substrate to align the electronic component with the concavity.
    Type: Application
    Filed: December 1, 2008
    Publication date: October 1, 2009
    Applicant: IBIDEN CO., LTD.
    Inventor: Hironori Tanaka
  • Publication number: 20090231820
    Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer, a first electrode and a second electrode, the high dielectric layer being interposed between the first and second electrodes. A plurality of resin insulating layers are formed on the insulating layer and include an upper resin insulating layer provided on a first electrode side of the capacitor, and a lower resin insulating layer provided on a second electrode side of the capacitor. A semiconductor device mounting pad includes a first pad and a second pad, the semiconductor device mounting pad being formed on an outermost resin insulating layer of the resin insulating layers, and a first via conductor is formed in at least one of the resin insulating layers to electrically connect the first pad with the first electrode.
    Type: Application
    Filed: January 22, 2009
    Publication date: September 17, 2009
    Applicant: IBIDEN CO., LTD.
    Inventor: Hironori Tanaka
  • Patent number: 7578625
    Abstract: An optical fiber array 10 includes: a substrate 30 with housing grooves 34 for housing optical fibers 24 formed therein; a cover plate 12 for covering the optical fibers 24 that are housed in the housing grooves 34; and an adhesive layer 16 for joining the substrate 30 with the optical fibers 24 being housed in the housing grooves 34 and the coverplate 12. In the substrate 30, there are formed adhesive grooves 36 for introduction of the adhesive layer 16 between the housing grooves 34 for housing the optical fibers 24 and the end portions of the substrate 30.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 25, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Hironori Tanaka, Naoaki Fujii
  • Publication number: 20090205859
    Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Application
    Filed: January 12, 2009
    Publication date: August 20, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Publication number: 20090205202
    Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Application
    Filed: January 12, 2009
    Publication date: August 20, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
  • Publication number: 20090193335
    Abstract: A document management device, which includes: a document receptor that receives a document; a pattern information generator that generates first information on which a first background pattern image is based; an addition section that adds the first information to the document; a setter that sets, to the document, a prohibition on editing the first information; a document storage that stores the document having the first information added thereto; a printing request receptor that receives a printing request; an prohibition lifting section that lifts the prohibition; an edition section that edits the first information to make second information on which a second background pattern image is based; a printing image generator that generates a printing image having the second background pattern image incorporated thereinto; and a sender that sends, to an image formation device, the printing image having the second background pattern image incorporated thereinto.
    Type: Application
    Filed: January 21, 2009
    Publication date: July 30, 2009
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Hironori TANAKA, Takahiro SAITO, Shintaro KOJO, Yukio IIJIMA, Hajime ICHIDA, Yuka AOKI, Noriyuki KAJITANI
  • Publication number: 20090145643
    Abstract: A printed wiring board with a built-in resistive element comprising a first electrode formed on the surface of an insulating member, a second electrode provided adjacent to the first electrode to form a space therebetween, a resistor-filling part formed by the space between the first electrode and the second electrode, and a resistive element comprising a resistive material provided in the resistor-filling part wherein the resistor-filling part is substantially enclosed by the first electrode and the second electrode.
    Type: Application
    Filed: July 2, 2008
    Publication date: June 11, 2009
    Applicant: IBIDEN CO., LTD.
    Inventor: Hironori Tanaka