Patents by Inventor Hiroshi Ono

Hiroshi Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563114
    Abstract: According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 24, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Matthew David Smith, Hiroshi Ono, Yosuke Kajiwara, Akira Mukai, Masahiko Kuraguchi
  • Patent number: 11560517
    Abstract: A photoreactive liquid crystal composition containing (A) a photoreactive polymer liquid crystal which includes a photoreactive side chain in which at least one type of reaction selected from (A-1) photocrosslinking and (A-2) photoisomerization occurs, and (B) a low molecular weight liquid crystal. An optical element or display element is formed having a liquid crystal cell including the photoreactive liquid crystal composition.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: January 24, 2023
    Assignees: UNIVERSITY OF HYOGO, NAGAOKA UNIVERSITY OF TECHNOLOGY, NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tomoyuki Sasaki, Hiroshi Ono, Nobuhiro Kawatsuki, Kohei Goto
  • Patent number: 11545553
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 3, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Hikosaka, Hiroshi Ono, Jumpei Tajima, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 11524284
    Abstract: An exhaust gas purification device has a metal substrate and a catalyst layer on the metal substrate, wherein the metal substrate is a wound body of one or a plurality of metal foils, at least one of the one or a plurality of metal foils is a perforated metal foil having holes, the catalyst layer contains noble metal catalyst particles and a carrier for carrying the noble metal catalyst particles, and more noble metal catalyst particles are present in the catalyst layer on side surfaces of holes, which face an upstream side of an exhaust gas flow, than in the catalyst layer on side surfaces of holes, which face a downstream side of the exhaust gas flow.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: December 13, 2022
    Assignee: CATALER CORPORATION
    Inventors: Kohei Takasaki, Yuji Matsuhisa, Nobuaki Bando, Hiroshi Ono, Tomohito Mizukami, Tsuyoshi Ito
  • Publication number: 20220388216
    Abstract: The subject of the present invention is to provide a resin material in which woody biomass and a thermoplastic resin are uniformly mixed, and which is easy to mold. The present invention provides a molding resin material containing a pulverized product from a woody biomass-derived torrefied product and a thermoplastic resin.
    Type: Application
    Filed: December 10, 2020
    Publication date: December 8, 2022
    Inventors: Hiroshi Ono, Kei Matsumoto, Yoichi Ishino, Koichi Kimura
  • Publication number: 20220336630
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a first conductive member, a first electrode, a first insulating member, and a second insulating member. The semiconductor member includes a first partial region, a second partial region, and a third partial region. The first partial region is between the second partial region the third partial region. The first conductive member includes a first conductive portion. The first conductive portion is between the second partial region and the third partial region. The first electrode is electrically connected to the first conductive member. The first electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first insulating member includes a first insulating region, a second insulating region, and a third insulating region. The second insulating member includes a first insulating portion and a second insulating portion.
    Type: Application
    Filed: November 10, 2021
    Publication date: October 20, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi ONO, Yosuke KAJIWARA, Masahiko KURAGUCHI
  • Patent number: 11476336
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, and a first compound member. A position of the third electrode is between a position of the second electrode and a position of the first electrode. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the third and first partial regions. The fifth partial region is between the second and third partial regions. The second semiconductor layer includes first, second, and third semiconductor regions. The third semiconductor region is between the first partial region and the first electrode. The first compound member includes first compound portions between the third semiconductor region and the first electrode. A portion of the first electrode is between one of the first compound portions and an other one of the first compound portions.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Ono, Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Aya Shindome, Masahiko Kuraguchi
  • Publication number: 20220310301
    Abstract: In the multi-layer inductor, all of the plurality of through conductors are not aligned in a straight line, and the distance between the through conductors can be sufficiently kept in the element body having a predetermined dimensional standard. Therefore, the through conductor as a heat source is apart from each other, and the heat of the through conductor can be efficiently radiated to the outside of the element body.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 29, 2022
    Applicant: TDK Corporation
    Inventors: Akihiko OIDE, Makoto YOSHINO, Tomoki OKADA, Seiji OSADA, Yuuki OKAZAKI, Takeshi SASAKI, Mitsuru ITO, Kenta SASAKI, Kazuhiro EBINA, Takashi ABE, Hiroshi ONO
  • Publication number: 20220310299
    Abstract: In the multi-layer inductor, the internal electrode includes the auxiliary conductor, and the auxiliary conductor is jointed to the external electrode at the end face. Therefore, when a defect occurs in a part of the through conductors, a current flows through the remaining through conductor(s) and a current also flows through the auxiliary conductor. Therefore, overheating at the joint surface between the remaining through conductor(s) and the external electrode can be prevented, and cutting and/or fusion starting from the joint surface can be prevented.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 29, 2022
    Applicant: TDK Corporation
    Inventors: Akihiko OIDE, Makoto YOSHINO, Tomoki OKADA, Seiji OSADA, Yuuki OKAZAKI, Takeshi SASAKI, Mitsuru ITO, Kenta SASAKI, Kazuhiro EBINA, Takashi ABE, Hiroshi ONO
  • Publication number: 20220231155
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, first and second insulating members. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes a first insulating portion. The first insulating portion is between the third and first electrode portions. The second insulating member includes first and second insulating regions. The first insulating region is between the first electrode and the first electrode portion. The second insulating region is between the first insulating region and the first electrode portion.
    Type: Application
    Filed: August 10, 2021
    Publication date: July 21, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KAJIWARA, Hiroshi ONO, Daimotsu KATO, Akira MUKAI, Masahiko KURAGUCHI
  • Publication number: 20220190150
    Abstract: According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions.
    Type: Application
    Filed: January 26, 2021
    Publication date: June 16, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Matthew David SMITH, Hiroshi ONO, Yosuke KAJIWARA, Akira MUKAI, Masahiko KURAGUCHI
  • Patent number: 11335839
    Abstract: The object of the present invention is to provide a Group III nitride semiconductor light emitting diode having improved light extraction efficiency. A Group III nitride semiconductor light emitting diode according to the present disclosure includes an RAMO4 layer including a single crystal represented by the general formula RAMO4 (wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd); and a layered product stacked on the RAMO4 layer. The layered product includes at least a light emitting layer including a Group III nitride semiconductor.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 17, 2022
    Assignee: PANASONIC CORPORATION
    Inventors: Hiroshi Ono, Kenya Yamashita, Akihiko Ishibashi
  • Publication number: 20220145132
    Abstract: A polishing liquid for CMP, containing: abrasive grains containing silica; and a liquid medium, in which a content of the abrasive grains is 1.0% by mass or more based on the total amount of the polishing liquid, and in a particle size distribution on mass basis obtained by a centrifugation method, D50 of the abrasive grains is 150 nm or less, D90 of the abrasive grains is 100 nm or more, and a difference between the D90 and the D50 is 21 nm or more.
    Type: Application
    Filed: June 2, 2020
    Publication date: May 12, 2022
    Inventors: Keisuke INOUE, Hiroshi ONO
  • Publication number: 20220140125
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2—1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daimotsu KATO, Hiroshi ONO, Tatsuo SHIMIZU, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI
  • Publication number: 20220130986
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2?1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.
    Type: Application
    Filed: August 12, 2021
    Publication date: April 28, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daimotsu KATO, Hiroshi ONO, Tatsuo SHIMIZU, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI
  • Publication number: 20220102512
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.
    Type: Application
    Filed: November 3, 2021
    Publication date: March 31, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki HIKOSAKA, Hiroshi ONO, Jumpei TAJIMA, Masahiko KURAGUCHI, Shinya NUNOUE
  • Patent number: 11251293
    Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, and an insulating part. The third electrode is between the first and second electrodes in a first direction from the first electrode toward the second electrode. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. A second direction from the first partial region toward the first electrode crosses the first direction. The second semiconductor region includes Alx2Ga1-x2N and includes sixth and seventh partial regions. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region between the fifth and seventh partial regions. The fourth semiconductor region includes Alx4Ga1-x4N and includes a first portion between the fifth and eighth partial regions. The fourth semiconductor region includes a first element not included the first to third semiconductor regions. The insulating part includes first to third insulating regions.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 15, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Kajiwara, Hiroshi Ono, Jumpei Tajima, Toshiki Hikosaka, Shinya Nunoue, Masahiko Kuraguchi
  • Patent number: 11225389
    Abstract: An image forming apparatus includes a main body, a sheet cassette attachable to the main body and configured to support one or more sheets to be supplied to the image forming unit, and a controller. The main body includes an electrode movable relative to the main body, a capacitance detector configured to output a signal indicating a value corresponding to a quantity of electricity stored in the electrode, and a wire. The sheet cassette includes a metal member, and a sheet supporting plate made of metal, movable relative to the sheet cassette in an up-down direction, and configured to support one or more sheets from below. The controller is configured to determine whether the sheet cassette is at an installation position in the main body from a level of the value of the signal outputted from the capacitance detector connected to the electrode via the wire.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 18, 2022
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hiroshi Ono
  • Publication number: 20220007911
    Abstract: The present invention provides a manual cleaning tool that enables suppression of plastic deformation (permanent deformation) such as bending when a roller brush is removed. The present invention includes a roller brush (7) provided in a frame main body (15). The roller brush (7) includes a rigid shaft (46), a pair of guide rollers (47, 48), which are arranged concentrically with a shaft center line (G) of the rigid shaft (46), and are mounted to shaft ends (46A, 46B) of the rigid shaft (46), and a cleaning brush cloth (49) including cut piles (52) raised from a cloth front surface (51A) of a foundation cloth (51). The cleaning brush cloth (49) is helically wound around a shaft outer-peripheral surface (46C) of the rigid shaft (46) with a cloth back surface (51B) of the foundation cloth (51) being in contact with the shaft outer-peripheral surface (46C), and is fixed to the rigid shaft. The roller brush (7) is removable from the frame main body (15) under an elastically deformed state of the rigid shaft (46).
    Type: Application
    Filed: May 16, 2019
    Publication date: January 13, 2022
    Inventors: Hiroshi Ono, Yusuke Hino, Tsutomu Sato, Rio Otsuru, Keiko Nishimura, Ryo Iriguchi
  • Patent number: 11211463
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 28, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Hikosaka, Hiroshi Ono, Jumpei Tajima, Masahiko Kuraguchi, Shinya Nunoue