Patents by Inventor Hiroshi Ono
Hiroshi Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220190150Abstract: According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions.Type: ApplicationFiled: January 26, 2021Publication date: June 16, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Matthew David SMITH, Hiroshi ONO, Yosuke KAJIWARA, Akira MUKAI, Masahiko KURAGUCHI
-
Patent number: 11335839Abstract: The object of the present invention is to provide a Group III nitride semiconductor light emitting diode having improved light extraction efficiency. A Group III nitride semiconductor light emitting diode according to the present disclosure includes an RAMO4 layer including a single crystal represented by the general formula RAMO4 (wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd); and a layered product stacked on the RAMO4 layer. The layered product includes at least a light emitting layer including a Group III nitride semiconductor.Type: GrantFiled: July 9, 2019Date of Patent: May 17, 2022Assignee: PANASONIC CORPORATIONInventors: Hiroshi Ono, Kenya Yamashita, Akihiko Ishibashi
-
Publication number: 20220145132Abstract: A polishing liquid for CMP, containing: abrasive grains containing silica; and a liquid medium, in which a content of the abrasive grains is 1.0% by mass or more based on the total amount of the polishing liquid, and in a particle size distribution on mass basis obtained by a centrifugation method, D50 of the abrasive grains is 150 nm or less, D90 of the abrasive grains is 100 nm or more, and a difference between the D90 and the D50 is 21 nm or more.Type: ApplicationFiled: June 2, 2020Publication date: May 12, 2022Inventors: Keisuke INOUE, Hiroshi ONO
-
Publication number: 20220140125Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2—1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daimotsu KATO, Hiroshi ONO, Tatsuo SHIMIZU, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI
-
Publication number: 20220130986Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2?1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.Type: ApplicationFiled: August 12, 2021Publication date: April 28, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daimotsu KATO, Hiroshi ONO, Tatsuo SHIMIZU, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI
-
Publication number: 20220102512Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.Type: ApplicationFiled: November 3, 2021Publication date: March 31, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki HIKOSAKA, Hiroshi ONO, Jumpei TAJIMA, Masahiko KURAGUCHI, Shinya NUNOUE
-
Patent number: 11251293Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, and an insulating part. The third electrode is between the first and second electrodes in a first direction from the first electrode toward the second electrode. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. A second direction from the first partial region toward the first electrode crosses the first direction. The second semiconductor region includes Alx2Ga1-x2N and includes sixth and seventh partial regions. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region between the fifth and seventh partial regions. The fourth semiconductor region includes Alx4Ga1-x4N and includes a first portion between the fifth and eighth partial regions. The fourth semiconductor region includes a first element not included the first to third semiconductor regions. The insulating part includes first to third insulating regions.Type: GrantFiled: February 26, 2020Date of Patent: February 15, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yosuke Kajiwara, Hiroshi Ono, Jumpei Tajima, Toshiki Hikosaka, Shinya Nunoue, Masahiko Kuraguchi
-
Patent number: 11225389Abstract: An image forming apparatus includes a main body, a sheet cassette attachable to the main body and configured to support one or more sheets to be supplied to the image forming unit, and a controller. The main body includes an electrode movable relative to the main body, a capacitance detector configured to output a signal indicating a value corresponding to a quantity of electricity stored in the electrode, and a wire. The sheet cassette includes a metal member, and a sheet supporting plate made of metal, movable relative to the sheet cassette in an up-down direction, and configured to support one or more sheets from below. The controller is configured to determine whether the sheet cassette is at an installation position in the main body from a level of the value of the signal outputted from the capacitance detector connected to the electrode via the wire.Type: GrantFiled: November 26, 2019Date of Patent: January 18, 2022Assignee: Brother Kogyo Kabushiki KaishaInventor: Hiroshi Ono
-
Publication number: 20220007911Abstract: The present invention provides a manual cleaning tool that enables suppression of plastic deformation (permanent deformation) such as bending when a roller brush is removed. The present invention includes a roller brush (7) provided in a frame main body (15). The roller brush (7) includes a rigid shaft (46), a pair of guide rollers (47, 48), which are arranged concentrically with a shaft center line (G) of the rigid shaft (46), and are mounted to shaft ends (46A, 46B) of the rigid shaft (46), and a cleaning brush cloth (49) including cut piles (52) raised from a cloth front surface (51A) of a foundation cloth (51). The cleaning brush cloth (49) is helically wound around a shaft outer-peripheral surface (46C) of the rigid shaft (46) with a cloth back surface (51B) of the foundation cloth (51) being in contact with the shaft outer-peripheral surface (46C), and is fixed to the rigid shaft. The roller brush (7) is removable from the frame main body (15) under an elastically deformed state of the rigid shaft (46).Type: ApplicationFiled: May 16, 2019Publication date: January 13, 2022Inventors: Hiroshi Ono, Yusuke Hino, Tsutomu Sato, Rio Otsuru, Keiko Nishimura, Ryo Iriguchi
-
Patent number: 11211463Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.Type: GrantFiled: February 25, 2020Date of Patent: December 28, 2021Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Hikosaka, Hiroshi Ono, Jumpei Tajima, Masahiko Kuraguchi, Shinya Nunoue
-
Publication number: 20210384337Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.Type: ApplicationFiled: August 20, 2021Publication date: December 9, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Daimotsu KATO, Yosuke KAJIWARA, Akira MUKAI, Aya SHINDOME, Hiroshi ONO, Masahiko KURAGUCHI
-
Patent number: 11189718Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first conductive part, first and second insulating layers. The third electrode includes first and second portions. The first portion is between the first electrode and the second electrode. The first semiconductor layer includes first, second, third, fourth and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor layer includes first and second semiconductor regions. The first conductive part is electrically connected to the first electrode. The first insulating layer includes a first insulating portion. The second insulating layer includes first and second insulating regions.Type: GrantFiled: February 25, 2020Date of Patent: November 30, 2021Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
-
Patent number: 11139393Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1-x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1-x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1-x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.Type: GrantFiled: September 12, 2019Date of Patent: October 5, 2021Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
-
Patent number: 11136474Abstract: A polishing liquid for polishing a surface to be polished containing a tungsten material, the polishing liquid comprising abrasive grains; a polymer having a cationic group at the terminal; an oxidizing agent; a metal oxide-dissolving agent; and water, in which the polymer has a structural unit derived from an unsaturated carboxylic acid, a weight average molecular weight of the polymer is 20000 or less, and a pH is less than 5.0.Type: GrantFiled: January 23, 2018Date of Patent: October 5, 2021Assignee: Showa Denko Materials Co., Ltd.Inventors: Hiroshi Ono, Makoto Mizutani
-
Publication number: 20210286265Abstract: A photosensitive element comprising a support film, a barrier layer, and a photosensitive layer in this order, wherein the barrier layer contains a water-soluble resin and an ultraviolet absorber.Type: ApplicationFiled: May 8, 2019Publication date: September 16, 2021Inventors: Masakazu KUME, Hiroshi ONO
-
Publication number: 20210257243Abstract: An electrostatic chuck of the disclosure includes a ceramic base in plate form, and an electrostatic attraction electrode. The ceramic base includes a plurality of particles containing aluminum oxide as a main component. The plurality of particles contain magnesium atoms and zirconium atoms.Type: ApplicationFiled: August 27, 2019Publication date: August 19, 2021Applicant: KYOCERA CorporationInventor: Hiroshi ONO
-
Publication number: 20210256867Abstract: A driving simulator with which a person with impaired vision can accurately recognize danger at driving and influence of a visual field loss on driving can be experienced is provided. A controller (6) of this driving simulator (1) executes simulated video display control to store visual field loss information data of a user M and simulated video data and display the simulated video data on a screen (8). The controller (6) stores association video data in which a viewpoint O of the user M, the visual field loss information data, and a video of an object in the simulated video data are associated with one another being centered at the viewpoint O of the user M in an identical video during execution of the simulated video display control, and performs playback display of the association video data on the screen (8) after end of the simulated video display control.Type: ApplicationFiled: July 18, 2019Publication date: August 19, 2021Inventors: Junpei KUWANA, Hiroshi ONO, Makoto ITO
-
Patent number: 11088269Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region includes Alx1Ga1-x1N. The first nitride region includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second nitride region includes Alx2Ga1-x2N. The second nitride region includes sixth and seventh partial regions. The first insulating film includes a first insulating region and is between the third partial region and the third electrode. The third partial region has a first surface opposing the first insulating region. The fourth partial region has a second surface opposing the sixth partial region.Type: GrantFiled: March 3, 2020Date of Patent: August 10, 2021Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
-
Publication number: 20210234012Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride member. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The nitride member includes a first nitride layer and a second nitride layer. The first nitride layer includes first, second, and third partial regions. The first electrode includes first, second, and third conductive portions, and a first conductive layer. The first, second, third conductive portions, and a portion of the second nitride layer are between the first partial region and the first conductive layer. The first, second, and third conductive portions are electrically connected to the first conductive layer. The second nitride layer includes a first region between the first and second conductive portions.Type: ApplicationFiled: September 9, 2020Publication date: July 29, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Hiroshi ONO, Yosuke KAJIWARA, Masahiko KURAGUCHI
-
Patent number: 11019233Abstract: An optical scanning device includes a controller, and a scanning unit connected with the controller via a signal line. The scanning unit includes a semiconductor laser having light emitting elements, an optical system configured to convert light emitted by each light emitting element into a beam, a deflector configured to deflect the beam received through the optical system, and a shift register including a plurality of output terminals each configured to output a light emission signal for controlling light emission from a corresponding one of the light emitting elements, and an input terminal configured to receive a shift signal from the controller via the signal line. The shift register is configured to, each time receiving the shift signal via the input terminal, shift a specific output terminal to output the light emission signal from one output terminal to another in sequence among the plurality of output terminals.Type: GrantFiled: March 10, 2020Date of Patent: May 25, 2021Assignee: Brother Kogyo Kabushiki KaishaInventors: Takato Mori, Hiroshi Ono, Kunihiro Amano