Patents by Inventor Hiroshi Ono

Hiroshi Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135447
    Abstract: A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO4 substrate including a single crystal represented by the general formula RAMO4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.
    Type: Application
    Filed: September 6, 2019
    Publication date: April 30, 2020
    Inventors: Akihiko ISHIBASHI, Hiroshi ONO, Kenya YAMASHITA
  • Patent number: 10600900
    Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 24, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Tatsuo Shimizu, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10535744
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: January 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Publication number: 20200014431
    Abstract: The object of the present invention is to provide a Group III nitride semiconductor light emitting diode having improved light extraction efficiency. A Group III nitride semiconductor light emitting diode according to the present disclosure includes an RAMO4 layer including a single crystal represented by the general formula RAMO4 (wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd); and a layered product stacked on the RAMO4 layer. The layered product includes at least a light emitting layer including a Group III nitride semiconductor.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 9, 2020
    Applicant: Panasonic Corporation
    Inventors: Hiroshi ONO, Kenya YAMASHITA, Akihiko ISHIBASHI
  • Publication number: 20190386127
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first insulating film. The first semiconductor region includes a first partial region, a second partial region, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second semiconductor region includes a sixth partial region and a seventh partial region. The third electrode overlaps the sixth and seventh partial regions. The first insulating film includes a portion provided between the third electrode and the third partial region, between the third electrode and the fourth partial region, between the third electrode and the fifth partial region, between the third electrode and the sixth partial region, and between the third electrode and the seventh partial region.
    Type: Application
    Filed: March 11, 2019
    Publication date: December 19, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daimotsu KATO, Toshiya Yonehara, Hiroshi Ono, Yosuke Kajiwara, Masahiko Kuraguchi, Tatsuo Shimizu
  • Publication number: 20190371928
    Abstract: According to one embodiment, a semiconductor device includes first and second regions, a first insulating portion, and first, second, and third electrodes. The first region includes first and second partial regions, and a third partial region between the first and second partial regions. The second region includes fourth and fifth partial regions. The fourth partial region overlaps the first partial region. The fifth partial region overlaps the second partial region. The first insulating portion includes first, second, and third insulating regions. The first insulating region is provided between the second insulating region and the third partial region and between the third insulating region and the third partial region. The first electrode is electrically connected to the fourth partial region. The second electrode is away from the first electrode and is electrically connected to the fifth partial region. The third electrode is provided between the first and second electrodes.
    Type: Application
    Filed: March 5, 2019
    Publication date: December 5, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko KURAGUCHI, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Publication number: 20190352537
    Abstract: A polishing liquid for polishing a surface to be polished containing a tungsten material, the polishing liquid comprising abrasive grains; a polymer having a cationic group at the terminal; an oxidizing agent; a metal oxide-dissolving agent; and water, in which the polymer has a structural unit derived from an unsaturated carboxylic acid, a weight average molecular weight of the polymer is 20000 or less, and a pH is less than 5.0.
    Type: Application
    Filed: January 23, 2018
    Publication date: November 21, 2019
    Inventors: Hiroshi ONO, Makoto MIZUTANI
  • Patent number: 10473075
    Abstract: An objective of the present invention is to provide a fuel rail that can be used at a high fuel pressure of 50 MPa or more, for example, has good engine mountability, and has improved material yield.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 12, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Eiichi Kubota, Koji Harada, Keiichi Uraki, Shinya Nakatani, Hiroshi Ono, Masahiro Soma
  • Publication number: 20190280667
    Abstract: A multilayer LC filter array includes an element body of a rectangular parallelepiped shape, a first filter including a first inductor and a first capacitor that are disposed in the element body, a second filter including a second inductor and a second capacitor that are disposed in the element body, a first input terminal electrode and a first output terminal electrode that are connected to the first inductor, a second input terminal electrode and a second output terminal electrode that are connected to the second inductor, and a ground terminal electrode that is connected to the first capacitor and the second capacitor. The element body includes first and second principal surfaces opposing each other. The ground terminal electrode is disposed at a center of the first principal surface.
    Type: Application
    Filed: August 21, 2017
    Publication date: September 12, 2019
    Applicant: TDK CORPORATION
    Inventors: Akihiko OIDE, Naoki UCHIDA, Yoji TOZAWA, Makoto YOSHINO, Seiichi NAKAGAWA, Shinichi SATO, Hiroshi ONO, Takashi ENDO
  • Patent number: 10401766
    Abstract: An image forming apparatus includes a fixing rotator rotatable in a predetermined direction of rotation, over which a recording medium is conveyed, and a heater to heat the fixing rotator. A temperature detector detects a temperature of the fixing rotator. A controller performs a primary productivity control to define a primary productivity rate of printing per unit time based on the temperature of the fixing rotator that is detected by the temperature detector. The controller calculates an amount of power suppliable to the heater and performs a secondary productivity control simultaneously with and separately from the primary productivity control. The secondary productivity control defines a secondary productivity rate of printing per unit time based on the amount of power suppliable to the heater. The controller selects one of the primary productivity rate and the secondary productivity rate whichever is lower as a productivity rate of the image forming apparatus.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: September 3, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Ryohhei Sugiyama, Hiroshi Ono, Hironori Yamaoka, Motoyoshi Yamano, Yoshikuni Sasaki, Tetsuo Tokuda
  • Patent number: 10347734
    Abstract: A semiconductor device includes a nitride semiconductor layer, a first electrode and second electrode on the nitride semiconductor layer, a gate electrode, and a gate insulating layer between the nitride semiconductor layer and the gate electrode. The gate insulating layer has a first oxide region containing at least any one element of aluminum and boron, gallium, and silicon. When a distance between the first end portion and the second end portion of the first oxide region is defined as d1, and a position separated by d1/10 from the first end portion toward the second end portion is defined as a first position, an atomic concentration of gallium at the first position is 80% or more and 120% or less of that of the at least any one element.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito, Hiroshi Ono, Toshiya Yonehara
  • Publication number: 20190189758
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Toshiya YONEHARA, Hiroshi ONO, Daimotsu KATO, Akira MUKAI
  • Publication number: 20190115461
    Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.
    Type: Application
    Filed: August 31, 2018
    Publication date: April 18, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Tatsuo Shimizu, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10256308
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Publication number: 20190088771
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.
    Type: Application
    Filed: February 21, 2018
    Publication date: March 21, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Miki Yumoto, Hiroshi Ono
  • Patent number: 10211301
    Abstract: A semiconductor device according to an embodiment includes: a wide bandgap semiconductor layer; a gate electrode; and a gate insulating layer disposed between the wide bandgap semiconductor layer and the gate electrode, including a first silicon oxide film, a second silicon oxide film between the first silicon oxide film and the gate electrode, and a first aluminum oxynitride film between the first silicon oxide film and the second silicon oxide film, and having a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the first aluminum oxynitride film which is lower than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position, closer to the second silicon oxide film than the first position, in the first aluminum oxynitride film.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10153347
    Abstract: A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride semiconductor layer containing Ga, a first electrode and a second electrode provided on or above the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode provided between the first electrode and the second electrode, a conductive layer provided on or above the second electrode, of which a first distance to the second electrode is smaller than a second distance between the second electrode and the gate electrode, and which is electrically connected to the first electrode or the gate electrode, a first aluminum oxide layer provided between the gate electrode and the second electrode and provided between the second nitride semiconductor layer and the conductive layer, a silicon oxide layer, and a second aluminum oxide layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito, Hiroshi Ono
  • Publication number: 20180308950
    Abstract: A semiconductor device includes a nitride semiconductor layer, a first electrode and second electrode on the nitride semiconductor layer, a gate electrode, and a gate insulating layer between the nitride semiconductor layer and the gate electrode. The gate insulating layer has a first oxide region containing at least any one element of aluminum and boron, gallium, and silicon. When a distance between the first end portion and the second end portion of the first oxide region is defined as d1, and a position separated by d1/10 from the first end portion toward the second end portion is defined as a first position, an atomic concentration of gallium at the first position is 80% or more and 120% or less of that of the at least any one element.
    Type: Application
    Filed: February 6, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Hisashi SAITO, Hiroshi ONO, Toshiya YONEHARA
  • Publication number: 20180274507
    Abstract: An objective of the present invention is to provide a fuel rail that can be used at a high fuel pressure of 50 MPa or more, for example, has good engine mountability, and has improved material yield.
    Type: Application
    Filed: January 12, 2016
    Publication date: September 27, 2018
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Eiichi KUBOTA, Koji HARADA, Keiichi URAKI, Shinya NAKATANI, Hiroshi ONO, Masahiro SOMA
  • Publication number: 20180204916
    Abstract: A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride semiconductor layer containing Ga, a first electrode and a second electrode provided on or above the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode provided between the first electrode and the second electrode, a conductive layer provided on or above the second electrode, of which a first distance to the second electrode is smaller than a second distance between the second electrode and the gate electrode, and which is electrically connected to the first electrode or the gate electrode, a first aluminum oxide layer provided between the gate electrode and the second electrode and provided between the second nitride semiconductor layer and the conductive layer, a silicon oxide layer, and a second aluminum oxide layer.
    Type: Application
    Filed: September 5, 2017
    Publication date: July 19, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Hisashi SAITO, Hiroshi ONO