Patents by Inventor Hiroshi Ueda

Hiroshi Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180147815
    Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a resin film and a metal layer stacked on at least one of surfaces of the resin film. An average diffusion depth of a main metal of the metal layer in the resin film is 100 nm or less after a weather resistance test in which the substrate is held at 150° C. for seven days. The average diffusion depth is preferably 80 nm or less before the weather resistance test.
    Type: Application
    Filed: June 1, 2016
    Publication date: May 31, 2018
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kayo HASHIZUME, Yoshio OKA, Takashi KASUGA, Jinjoo PARK, Hiroshi UEDA
  • Publication number: 20180139460
    Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: Keisuke MATSUMOTO, Katsushige MATSUBARA, Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA
  • Patent number: 9967976
    Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a conductive layer formed on at least one of surfaces of the base film. In the substrate for a printed circuit board, at least the conductive layer contains titanium in a dispersed manner. The conductive layer preferably contains copper or a copper alloy as a main component. A mass ratio of titanium in the conductive layer is preferably 10 ppm or more and 1,000 ppm or less. The conductive layer is preferably formed by application and heating of a conductive ink containing metal particles. The conductive ink preferably contains titanium or a titanium ion. The metal particles are preferably obtained by a titanium redox process including reducing metal ions using trivalent titanium ions as a reducing agent in an aqueous solution by an action of the reducing agent.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 8, 2018
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kazuhiro Miyata, Issei Okada, Takashi Kasuga, Yoshio Oka, Yasuhiro Okuda, Jinjoo Park, Hiroshi Ueda, Kousuke Miura
  • Publication number: 20180124925
    Abstract: According to an embodiment of the present invention, a substrate for a printed circuit board, the substrate including a resin film and a metal layer deposited on at least one surface of the resin film, includes a modified layer on the surface of the resin film on which the metal layer is deposited, the modified layer having a composition different from another portion, in which the modified layer contains a metal, a metal ion, or a metal compound different from a main metal of the metal layer. The content of a metal element of the metal, the metal ion, or the metal compound on a surface of the modified layer is preferably 0.2 atomic % or more and 10 atomic % or less.
    Type: Application
    Filed: June 1, 2016
    Publication date: May 3, 2018
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kayo HASHIZUME, Yoshio OKA, Takashi KASUGA, Jinjoo PARK, Hiroshi UEDA
  • Patent number: 9946678
    Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Publication number: 20180077413
    Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 15, 2018
    Inventors: Kazushi AKIE, Seiji MOCHIZUKI, Toshiyuki KAYA, Katsushige MATSUBARA, Hiroshi UEDA, Ren IMAOKA, Ryoji HASHIMOTO
  • Patent number: 9916276
    Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 9906805
    Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Matsumoto, Katsushige Matsubara, Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda
  • Publication number: 20180054900
    Abstract: A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is ½ or more and 5 or less.
    Type: Application
    Filed: March 10, 2016
    Publication date: February 22, 2018
    Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Hiroshi UEDA, Kousuke MIURA, Yoshihito YAMAGUCHI, Yuka URABE
  • Publication number: 20180022769
    Abstract: A series of fluorine-containing bisphosphonic acids in which an alkylamine side chain is added, a series of fluorine-containing bisphosphonic acids in which an amino group substituted by a heterocyclic group or a heterocyclic group containing a nitrogen atom is added, to the carbon atom of P—C(F)—P, and a series of fluorine-containing bisphosphonate derivatives in which the acid moiety thereof is esterified by an alkoxymethyl group such as POM group, n-butanoyloxymethyl (BuOM) group and the like, that is, the fluorine-containing bisphosphonic acid and fluorine-containing bisphosphonate derivative represented by the following formula (I): wherein each symbol is as defined in the DESCRIPTION, can efficiently induce proliferation of peripheral blood ?? T cells that express V?2V?2 T cell receptor having superior cytotoxicity against tumor cells and virus infected cells, immunize tumor cells and virus infected cells, and can induce cytotoxicity by ?? T cells.
    Type: Application
    Filed: February 1, 2016
    Publication date: January 25, 2018
    Applicant: Nagasaki University
    Inventors: Yoshimasa TANAKA, Satoshi MIZUTA, Hiroshi UEDA
  • Publication number: 20180015547
    Abstract: An object of the present invention is to provide a metal powder and an ink with which a sintered body having good flexibility can be formed, and a sintered body having good flexibility. A metal powder according to an embodiment of the present invention has a mean particle size D50BET of 1 nm or more and 200 nm or less as calculated by a BET method, a mean crystallite size DCryst of 20 nm or less as determined by an X-ray analysis, and a ratio (DCryst/D50BET) of the mean crystallite size DCryst to the mean particle size D50BET of less than 0.4.
    Type: Application
    Filed: January 26, 2016
    Publication date: January 18, 2018
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Issei OKADA, Yoshio OKA, Takashi KASUGA, Yasuhiro OKUDA, Jinjoo PARK, Kousuke MIURA, Hiroshi UEDA
  • Publication number: 20180014403
    Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having insulating properties and a sintered layer formed of a plurality of metal particles, the sintered layer being stacked on at least one surface of the base film, in which a region of the sintered layer extending from an interface between the sintered layer and the base film to a position 500 nm or less from the interface has a porosity of 1% or more and 50% or less.
    Type: Application
    Filed: January 19, 2016
    Publication date: January 11, 2018
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Takashi KASUGA, Yoshio OKA, Shigeaki UEMURA, Jinjoo PARK, Hiroshi UEDA, Kousuke MIURA
  • Publication number: 20170359241
    Abstract: Provided are a communication system, an abnormality detection device and an abnormality detection method that detects abnormality concerning communication such as information forged by utilizing a difference in timings of sampling between multiple communication devices. For the system configuration where ECUs transmit and receive information through a common communication line, abnormality detection related to communication is performed by a monitoring device connected to the communication line. Each ECU receives information by sampling once at a predetermined timing during a transmission period of one-bit information. The ECUs may also be allowed to perform sampling at different timings.
    Type: Application
    Filed: January 13, 2016
    Publication date: December 14, 2017
    Inventors: Hiroaki Takada, Ryo Kurachi, Hiroshi Ueda
  • Publication number: 20170347464
    Abstract: An object is to provide a substrate for a printed wiring board that has good circuit formability while maintaining adhesion strength between a conductive layer (2) and a base film (1). The substrate includes a base film having an insulating property (1) and a conductive layer (2) formed on at least one surface of the base film (1). The maximum height Sz, which is defined in ISO25178, of the surface of the base film (1) is 0.05 ?m or more and less than 0.9 ?m.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 30, 2017
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kayo HASHIZUME, Yoshio OKA, Takashi KASUGA, Jinjoo PARK, Kousuke MIURA, Hiroshi UEDA
  • Publication number: 20170347449
    Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a metal layer formed on at least one surface side of the base film. In the substrate for a printed circuit board, a plurality of fine particles are disposed between the base film and the metal layer, and the fine particles are formed of a metal the same as a main metal of the metal layer or formed of a metal compound of the main metal. The fine particles preferably have an average particle size of 0.1 nm or more and 20 nm or less. The fine particles are preferably formed of a metal oxide or a metal hydroxide. The fine particles are preferably present between the base film and the metal layer so as to form a layer. The metal layer preferably includes a metal grain layer formed by firing metal nanoparticles.
    Type: Application
    Filed: December 18, 2015
    Publication date: November 30, 2017
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Motohiko SUGIURA, Takashi KASUGA, Yoshio OKA, Shigeaki UEMURA, Jinjoo PARK, Hiroshi UEDA, Kousuke MIURA
  • Publication number: 20170347459
    Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a conductive layer formed on at least one of surfaces of the base film. In the substrate for a printed circuit board, at least the conductive layer contains titanium in a dispersed manner. The conductive layer preferably contains copper or a copper alloy as a main component. A mass ratio of titanium in the conductive layer is preferably 10 ppm or more and 1,000 ppm or less. The conductive layer is preferably formed by application and heating of a conductive ink containing metal particles. The conductive ink preferably contains titanium or a titanium ion. The metal particles are preferably obtained by a titanium redox process including reducing metal ions using trivalent titanium ions as a reducing agent in an aqueous solution by an action of the reducing agent.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 30, 2017
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kazuhiro MIYATA, Issei OKADA, Takashi KASUGA, Yoshio OKA, Yasuhiro OKUDA, Jinjoo PARK, Hiroshi UEDA, Kousuke MIURA
  • Publication number: 20170337008
    Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 23, 2017
    Inventors: Seiji MOCHIZUKI, Katsushige Matsubara, Ren Imaoka, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Publication number: 20170290150
    Abstract: The substrate for a printed circuit board according to an embodiment of the present invention includes a base film having insulating properties, and a metal layer stacked on at least one surface of the base film, in which the base film includes a portion where a transition metal in group 10 of the periodic table is present. The transition metal in group 10 is preferably nickel or palladium. The portion where the transition metal in group 10 is present preferably includes a region having an average thickness of 500 nm and extending from an interface with the metal layer.
    Type: Application
    Filed: September 8, 2015
    Publication date: October 5, 2017
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Takashi KASUGA, Yoshio OKA, Shigeaki UEMURA, Shigeyoshi NAKAYAMA, Jinjoo PARK, Sumito UEHARA, Hiroshi UEDA, Kousuke MIURA
  • Publication number: 20170201166
    Abstract: Electric motor (100) according to the present invention includes stator (40), rotor (10), and a pair of bearings (30). Stator (40) has stator core (41) which is annularly formed. Rotor (10) is located on the inner circumferential side of stator core (41), and includes shaft (12), rotor core (11), and bonded magnets (14). Bonded magnets (14) are filled in magnet holes (13). Bonded magnets (14) are formed with high density portion (14b) having a high density and low density portion (14c) having a density lower than high density portion (14b). In electric motor (100), center position (11b) of rotor core (11) is located on the side where high density portion (14b) is present with respect to center position (41b) of stator core (41) in the direction of shaft center (12a) of shaft (12).
    Type: Application
    Filed: September 7, 2015
    Publication date: July 13, 2017
    Inventors: Takashi OGAWA, Yuichi YOSHIKAWA, Haruhiko KADO, Yukihiro OKADA, Hiroshi UEDA, Shin'ichi TSUTSUMI
  • Publication number: 20170135206
    Abstract: A printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a conductive pattern formed on at least one of surfaces of the base film, wherein at least a portion of the conductive pattern includes a core body, and a shrink layer formed by plating on an outer surface of the core body. The portion of the conductive pattern preferably has a striped configuration or a spiral configuration. The portion of the conductive pattern preferably has an average circuit gap width of 30 ?m or less. The portion of the conductive pattern preferably has an average aspect ratio of 0.5 or more. The plating is preferably electroplating or electroless plating.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 11, 2017
    Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Hiroshi UEDA, Kousuke MIURA