Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: A vertically alternating sequence of multi-fingered silicon-germanium layers and multi-fingered silicon layers is formed over a substrate. The multi-fingered silicon-germanium layers include silicon-germanium wires, and the multi-fingered silicon layers include silicon wires. Tubular memory films and multi-fingered gate electrodes are formed. Each gate electrode includes a respective gate electrode bar which overlies the silicon wires and a respective set of vertically-extending gate electrode fingers which is adjoined to a bottom portion of the respective gate electrode bar and spaced apart by the silicon wires. The multi-fingered silicon-germanium layers are removed selective to multi-fingered silicon layers. First active regions are formed at an end portion of each of the silicon wires. Second active regions are formed on silicon plate portions of the multi-fingered silicon layers.

Abstract: A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Abstract: A substrate processing apparatus, for generating a plasma from a gas by a high frequency energy and etching a substrate in a processing chamber by radicals in the plasma, includes a high frequency power supply configured to supply the high frequency energy into the processing chamber, a gas supply source configured to introduce the gas into the processing chamber, a mounting table configured to mount the substrate thereon, and a partition plate provided in the processing chamber and configured to divide an inner space of the processing chamber into a plasma generation space and a substrate processing space and suppress passage of ions therethrough. The partition plate and a portion of an inner wall surface of the processing chamber which is positioned at least above the mounting table are covered by a dielectric material having a recombination coefficient of 0.002 or less.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: A control device for a selectable one-way clutch includes a pocket plate; a notch plate rotating relative to the pocket plate; a selector plate between the pocket plate and the notch plate rotating coaxially with the notch plate to change between a state allowing engagement members to pass through respective openings and to stand up from a side close to the pocket plate toward a side close to the notch plate and a state allowing the housing recesses to house the engagement members; and a motion detection unit detecting a motion of the selector plate. Further, when an unintended motion of the selector plate is detected, the pocket plate and the notch plate to rotate differentially at a rotation speed equal to or less than a predetermined absolute value, and the selectable one-way clutch to fall into a state of ratchet or into a state of overrun.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: A cylindrical inner wall used in a substrate processing apparatus and surrounding a stage on which a substrate is placed, with a gap between the inner wall and an outer periphery of the stage. The inner wall includes a plurality of slits formed in a lower end of the inner wall, and a plurality of grooves formed in the inner surface of the inner wall to extend from an upper end to the lower end of the inner wall so as to communicate with the slits.

Abstract: A thermal actuator unit of the present invention includes a first member, a second member, an elastic part which is disposed between the first member and the second member, and a thermal deformation part which is disposed on a side of the first member opposite to a side with the second member and has a shape-memory alloy to be deformed to the side with the second member due to heat.

Abstract: In a substrate processing apparatus for processing a substrate mounted on a mounting table in a processing chamber by supplying a gas to the substrate, the apparatus includes: a partition unit provided, between a process space where a substrate is provided and a diffusion space where a first gas is diffused, to face the mounting table; a first as supply unit for supplying the first gas to the diffusion space; first gas injection holes, formed through the partition unit, for injecting the first gas diffused in the diffusion space into the processing space; and a second gas supply unit including second gas injection holes opened on a gas injection surface of the partition unit which faces the processing space. The second gas supply unit independently supplies a second gas to each of a plurality of regions arranged in a horizontal direction in the processing space separately from the first gas.

Abstract: An engaging device includes: inner and outer rings as two rotating elements; and an engaging piece, between the rings, projecting in a radial direction. Further, the engaging piece is attached to one of the rotating elements and another rotating element serves as an engaged member and movable in an axial direction, the engaging piece includes a first inclined portion in a tip end of a surface facing the another rotating element, the another rotating element includes a tapered portion, in a portion coming into contact with the first inclined portion, and in accordance with a position of the another rotating element, a state is switched between a one-way clutch state and a free state.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: A liquid crystal display device includes an array board, a CF board, detection electrodes, drive electrodes, and position detection lines. The array board includes TFTs in a display area and a display circuit that includes at least monolithic circuits in a non-display area. The CF board is opposed to the array board with a gap. The detection electrodes are arranged on an outer surface of the CF board in the display area to extend along the first direction. The drive electrodes are arranged on an inner surface of the CF board in the display area to extend along the second direction. The position detection lines are arranged on the inner surface of the CF board in the non-display area for transmitting signals to the drive electrodes. The position detection lines are arranged to overlap the monolithic circuits.

Abstract: In a substrate processing apparatus for processing a substrate mounted on a mounting table in a processing chamber by supplying a gas to the substrate, the apparatus includes: a partition unit provided, between a processing space where a substrate is provided and a diffusion space where a first gas is diffused, to face the mounting table; a first gas supply unit for supplying the first gas to the diffusion space; first gas injection holes, formed through the partition unit, for injecting the first gas diffused in the diffusion space into the processing space; and a second gas supply unit including second gas injection holes opened on a gas injection surface of the partition unit which faces the processing space. The second gas supply unit independently supplies a second gas to each of a plurality of regions arranged in a horizontal direction in the processing space separately from the first gas.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.