Abstract: A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.

Abstract: A display device is provided in which a configuration of first electrodes (4) in a first area (R1) that overlaps a display area (AA) of a touch panel (2), and a configuration of first electrodes (6) in a second area (R2) outside the first area, are different from each other. In the second area (R2), at least one electrode pad (6-1a, 6-2a) of the first electrodes (6) is arranged so as to be opposed to one second electrode (7a).

Abstract: A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

Abstract: A crystal display device 10 includes TFTs, pixel electrodes, common electrodes, an array board, a CF board, detection electrodes, drive electrodes , a driver, a row control circuit, and a touch controller. The detection electrodes are included in the CF board. The drive electrodes are included in the CF board. The driver and the row control circuit are included in a display driver portion for supplying scan signals and data signals to the TFTs for display driving. The touch controller supplies drive signals to the drive electrodes and detects position detection signals output by the detection electrodes to perform position detection control. The touch controller supplies the drive signals to the drive electrodes to drive the drive electrodes in a scan writing period in which the scan signals are supplied to the TFTs by at least the row control circuit in the display driver portion to drive the TFTs.

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.

Abstract: A CMOS device includes a p-type field effect transistor containing p-doped active regions, an n-type field effect transistor containing n-doped active regions, a silicon oxide layer overlying the n-type field effect transistor and not overlying the p-type field effect transistor, boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions, first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures, and second active region contact via structures contacting a top surface of a respective one of the n-doped active regions.

Abstract: An engaging device includes: inner and outer rings as two rotating elements; and an engaging piece, between the rings, projecting in a radial direction. Further, the engaging piece is attached to one of the rotating elements and another rotating element serves as an engaged member and movable in an axial direction, the engaging piece includes a first inclined portion in a tip end of a surface facing the another rotating element, the another rotating element includes a tapered portion, in a portion coming into contact with the first inclined portion, and in accordance with a position of the another rotating element, a state is switched between a one-way clutch state and a free state.

Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.

Abstract: A control device for a selectable one-way clutch includes a pocket plate; a notch plate rotating relative to the pocket plate; a selector plate between the pocket plate and the notch plate rotating coaxially with the notch plate to change between a state allowing engagement members to pass through respective openings and to stand up from a side close to the pocket plate toward a side close to the notch plate and a state allowing the housing recesses to house the engagement members; and a motion detection unit detecting a motion of the selector plate. Further, when an unintended motion of the selector plate is detected, the pocket plate and the notch plate to rotate differentially at a rotation speed equal to or less than a predetermined absolute value, and the selectable one-way clutch to fall into a state of ratchet or into a state of overrun.

Abstract: A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: A semiconductor structure, such as a CMOS device, includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first composite gate electrode containing a first vertical stack of a p-doped semiconductor gate electrode, a first interfacial dielectric layer, and a first metallic gate electrode. The second field effect transistor includes a second composite gate electrode containing a second vertical stack that includes an n-doped semiconductor gate electrode and a second metallic gate electrode. A second interfacial dielectric layer having a second thickness that is thinner than the first interfacial dielectric layer may, or may not, be present in the second composite gate electrode.

Abstract: A selectable one-way clutch includes: a pocket plate including pockets provided along a circumferential direction on one surface; a notch plate that is rotatable with respect to the pocket plate, the notch plate including notches provided along a circumferential direction on a surface facing the one surface; struts that are plate-shaped and housed in the respective pockets; and a selector plate disposed between the pocket plate and the notch plate, and configured to switch, by rotating coaxially with the pocket plate, between: a state in which the struts have risen toward the notch plate; and a state in which the struts are housed in the respective pockets. The notch plate includes flat portions between the notches that are adjacent in the circumferential direction, and each flat portion includes a first recess at a position where the corresponding strut having risen toward the notch plate is brought into contact.

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

Abstract: A power transmission apparatus for a vehicle includes an engagement mechanism and a switching mechanism. The switching mechanism includes: a hydraulic cylinder; a regulation valve regulates a hydraulic pressure to be supplied to a first oil chamber and a second oil chamber; a rocking valve switches a state of a hydraulic circuit between a closed circuit state and an open circuit state; and an oil pump supplies the hydraulic pressure to the hydraulic cylinder. The switching mechanism switches the engagement mechanism between an engaged state and a disengaged state after the hydraulic circuit is switched from the closed circuit state to the open circuit state by the rocking valve. The switching mechanism keeps the engaged state or the disengaged state of the engagement mechanism after switching the engaged state or the disengaged state of the engagement mechanism.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.