Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: A semiconductor structure, such as a CMOS device, includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first composite gate electrode containing a first vertical stack of a p-doped semiconductor gate electrode, a first interfacial dielectric layer, and a first metallic gate electrode. The second field effect transistor includes a second composite gate electrode containing a second vertical stack that includes an n-doped semiconductor gate electrode and a second metallic gate electrode. A second interfacial dielectric layer having a second thickness that is thinner than the first interfacial dielectric layer may, or may not, be present in the second composite gate electrode.

Abstract: A selectable one-way clutch includes: a pocket plate including pockets provided along a circumferential direction on one surface; a notch plate that is rotatable with respect to the pocket plate, the notch plate including notches provided along a circumferential direction on a surface facing the one surface; struts that are plate-shaped and housed in the respective pockets; and a selector plate disposed between the pocket plate and the notch plate, and configured to switch, by rotating coaxially with the pocket plate, between: a state in which the struts have risen toward the notch plate; and a state in which the struts are housed in the respective pockets. The notch plate includes flat portions between the notches that are adjacent in the circumferential direction, and each flat portion includes a first recess at a position where the corresponding strut having risen toward the notch plate is brought into contact.

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

Abstract: A power transmission apparatus for a vehicle includes an engagement mechanism and a switching mechanism. The switching mechanism includes: a hydraulic cylinder; a regulation valve regulates a hydraulic pressure to be supplied to a first oil chamber and a second oil chamber; a rocking valve switches a state of a hydraulic circuit between a closed circuit state and an open circuit state; and an oil pump supplies the hydraulic pressure to the hydraulic cylinder. The switching mechanism switches the engagement mechanism between an engaged state and a disengaged state after the hydraulic circuit is switched from the closed circuit state to the open circuit state by the rocking valve. The switching mechanism keeps the engaged state or the disengaged state of the engagement mechanism after switching the engaged state or the disengaged state of the engagement mechanism.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: A touch panel pattern TPP includes detection electrodes 38, driving electrodes 39, floating electrodes 45, and reference width floating electrode 48, a smallest width floating electrode 49, and an intermediate width floating electrode 50 that are included in the floating electrodes 45. The smallest width floating electrode 49 is disposed at an end-side one of the floating electrodes 45 with respect to a second direction and has a smallest width. The intermediate width floating electrode 50 is disposed closer to the end-side one than the reference width floating electrode 48 is and closer to a middle than the smallest width floating electrode 49 is and has a width FW2 smaller than that of the reference width floating electrode 48 and larger than that of the smallest width floating electrode 49.

Abstract: A touchscreen pattern includes detection electrodes, drive electrodes, floating electrodes, and wide detection electrodes. The detection electrodes extend along a first direction and are arranged along a second direction perpendicular to the first direction. The drive electrodes extend along the second direction and are arranged along the first direction to overlap the detection electrodes in a plan view. The drive electrodes and the detection electrodes form capacitors. The floating electrodes are arranged adjacent to the detection electrodes 38, respectively, in the plan view and to overlap the drive electrodes in the plan view. The floating electrodes and the adjacent detection electrodes form capacitors. The floating electrodes and the overlapping drive electrodes form capacitors. The wide detection electrodes are arranged at the outermost with respect to the second direction. The wide detection electrodes have a width larger than a width of the detection electrodes closer to the middle.

Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.

Abstract: A touch panel is realized that is able to decrease the amount of dead space at the periphery of the touch panel and that has highly accurate touch panel sensitivity. In a touch panel, Y direction conductive patterns are arranged so as to be separated from wiring patterns in Y direction conductive pattern regions between electrode units of X direction conductive patterns. As a result, in this conductive sheet, it is possible to appropriately prevent the occurrence of parasitic capacitance resulting from the Y direction conductive patterns and the wiring patterns. Therefore, in a touch panel device or the like that uses such a touch panel, it is possible to effectively prevent the generation of noise that overlaps sense signals as a result of the above-mentioned parasitic capacitance, thereby making it possible to realize highly accurate touch panel sensitivity.

Abstract: A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.

Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Abstract: A touch panel includes: a first substrate; a second substrate disposed on a viewer side of the first substrate; a liquid crystal layer provided between the first substrate and the second substrate; a plurality of pixel electrodes and a common electrode for applying a voltage to the liquid crystal layer; and a plurality of detection electrodes and a plurality of driving electrodes for a touch sensor. The first substrate includes: a first transparent substrate; and the plurality of pixel electrodes, which are formed on the liquid crystal layer side of the first transparent substrate. The second substrate includes: a second transparent substrate; and the plurality of driving electrodes and the plurality of detection electrodes formed on the liquid crystal layer side of the second transparent substrate. The touch panel does not include a conductive layer on the viewer side of the second transparent substrate.

Abstract: A liquid crystal display device includes an array board, a CF board, detection electrodes, drive electrodes, and position detection lines. The array board includes TFTs in a display area and a display circuit that includes at least monolithic circuits in a non-display area. The CF board is opposed to the array board with a gap. The detection electrodes are arranged on an outer surface of the CF board in the display area to extend along the first direction. The drive electrodes are arranged on an inner surface of the CF board in the display area to extend along the second direction. The position detection lines are arranged on the inner surface of the CF board in the non-display area for transmitting signals to the drive electrodes. The position detection lines are arranged to overlap the monolithic circuits.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures. Alternatively or additionally, the structural integrity of insulating layers during the replacement process can be enhanced by M×N array of semiconductor-containing support structures that extend through staircase region and having same materials as memory stack structures.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures. Alternatively or additionally, the structural integrity of insulating layers during the replacement process can be enhanced by M×N array of semiconductor-containing support structures that extend through staircase region and having same materials as memory stack structures.

Abstract: In a substrate processing apparatus for processing a substrate mounted on a mounting table in a processing chamber by supplying a gas to the substrate, the apparatus includes: a partition unit provided, between a processing space where a substrate is provided and a diffusion space where a first gas is diffused, to face the mounting table; a first gas supply unit for supplying the first gas to the diffusion space; first gas injection holes, formed through the partition unit, for injecting the first gas diffused in the diffusion space into the processing space; and a second gas supply unit including second gas injection holes opened on a gas injection surface of the partition unit which faces the processing space. The second gas supply unit independently supplies a second gas to each of a plurality of regions arranged in a horizontal direction in the processing space separately from the first gas.

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.