Abstract: A method for manufacturing a luggage formed by composite material includes the steps: A) using a vacuum molding method to make a thermoplastic sheet into a shell; B) placing the shell in an inner cavity mold area of a heating mold to correspond the outer surface of the shell to the inner wall surface of the inner cavity mold area; C) setting the outer surface of the thermosetting carbon fiber plastic layer on the inner surface of the shell ; D) setting the reinforcing layer on the inner surface of the thermosetting carbon fiber plastic layer at the location corresponding to the corner of the shell; and E) placing an airbag in the receiving area of the shell and inflating the airbag to support the inner surface of the thermosetting carbon fiber plastic layer and the reinforcing layer.

Abstract: The present invention provides compounds of Formula (I) which can be used as ACC inhibitors and potently as therapeutic agents against diseases mediated by ACC.

Abstract: A luggage shell fabrication method includes the step of making a thermoplastic sheet into a shell using a vacuum molding method, the step of placing the shell in a female mold area of a heating mold, the step of applying a molten thermosetting plastic layer to the inner surface of the shell; and the step of pressing the thermosetting plastic layer toward the inner surface of the shell and simultaneously heating the molten thermosetting plastic layer and the shell for causing the shell and the thermosetting plastic layer to be combined with each other to form a luggage shell.

Abstract: The present invention provides compounds of Formula (I) which can be used as ACC inhibitors and potently as therapeutic agents against diseases mediated by ACC.

Abstract: The invention relates to a method of increasing yield in plants comprising increasing the expression of a nucleic acid encoding a phosphate transporter (PT7) polypeptide. The invention also relates to methods of making such plants and genetically altered plants that display an increased yield.

Abstract: A luggage shell fabrication method includes the step of making a thermoplastic sheet into a shell using a vacuum molding method, the step of placing the shell in a female mold area of a heating mold, the step of applying a molten thermosetting plastic layer to the inner surface of the shell; and the step of pressing the thermosetting plastic layer toward the inner surface of the shell and simultaneously heating the molten thermosetting plastic layer and the shell for causing the shell and the thermosetting plastic layer to be combined with each other to form a luggage shell.

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first dielectric layer, a charge trapping layer, a ferroelectric material layer, and a gate layer. The first dielectric layer is disposed on the substrate, the charge trapping layer is disposed on the first dielectric layer, the ferroelectric material layer is disposed on the charge trapping layer, and the gate layer is disposed on the ferroelectric material layer.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region surrounding the first region; forming a gate stack and a dummy gate stack in the first region, wherein the dummy gate stack surrounds the gate stack; forming an oxide layer on an exterior wall and a top surface of the dummy gate stack; forming a dummy conductive layer on the gate stack, the dummy gate stack and the oxide layer, wherein the dummy conductive layer has a concave bowl-shaped top surface in the first region; and performing a chemical mechanical polishing (CMP) process on the dummy conductive layer.

Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.

Abstract: A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least one light-absorbing film above the floating gate, wherein at least one light-absorbing film is provided with dummy via holes overlapping the floating gate, and a dielectric layer on the light-absorbing film and filling up the dummy via holes.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

Abstract: A carry-on luggage includes a housing composed of a right half shell and a left half shell, each half shell including a base layer made from a thermosetting polymeric material (TS) by molding and a protective layer made from a thermoplastic polymeric material (TP) and molded on the outer surface of the base layer. Thus, the housing of the carry-on luggage has excellent impact resistance and toughness.

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

Abstract: A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one protruding portion. The first source having a first conductivity type is formed on the substrate. The drain having the first conductivity type is disposed on the protruding portion. The first gate electrode is disposed adjacent to a first sidewall of the protruding portion. The first gate dielectric layer is disposed between the first gate electrode and the first sidewall as well as being disposed adjacent to the first source and the drain. The first doping region having a second conductivity type is formed beneath the protruding portion and adjacent to the first source.