Patents by Inventor Hong Yu

Hong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119825
    Abstract: Apparatus, methods, and computer-readable media for facilitating determining or predicting a communication state of a UE based on, for example, measurements performed at the UE are disclosed herein. The communication state of the UE, such as an HST state or a non-HST state, may also be associated with a mobility state, such as stationary or moving. The UE may communicate based on the communication state. An example method for wireless communication at a UE includes establishing a connection with a network node. The example method also includes measuring one or more signals received from the network node over a time period. The example method also includes communicating with the network node based on a communication state of the UE, the communication state of the UE based at least in part on a history of measurements performed on the one or more signals received over the time period.
    Type: Application
    Filed: March 29, 2022
    Publication date: April 10, 2025
    Inventors: Jie MAO, Hong YU, Wei LI, Nanrun WU, Jie ZHU, Xinyu WANG, Tom CHIN
  • Patent number: 12268674
    Abstract: Mi-2? inhibitors and methods of using the same are disclosed. The methods comprise administering an effective amount of a Mi-2? inhibitor to the subject or contacting a cancer cell or a tumor with an effective amount of a Mi-2? inhibitor.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: April 8, 2025
    Assignee: BioVentures, LLC
    Inventors: Hong-yu Li, Zhengyu Wang, Jingwei Shao, Rutao Cui
  • Patent number: 12272740
    Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: April 8, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Haiting Wang, Hong Yu, Zhenyu Hu
  • Publication number: 20250108127
    Abstract: A modified vector of adenovirus-associated virus serotype 8 (AAV-8) for gene targeting and expression is provided, wherein the modified vector includes serotype coat amino acid sequence, insertion site and insertion amino acid sequence. A 10-amino acid sequence set forth in SEQ ID NO. 3 is inserted between amino acids at positions 590 and 591 that are set forth in SEQ ID NO. 2 of the AAV-8 serotype coat protein: LARGDSTKSA, wherein amino acids at positions 1, 2 and 10 are protective amino acids, and amino acids at positions 3 to 9 are screened amino acid sequences. In addition, the present invention also discloses construction method and application of the modified vector. The modified vector of the present invention has stronger fluorescence, can be observed obviously and intuitively. Exogenous gene can be efficiently expressed in the targeted tissues in vivo.
    Type: Application
    Filed: August 29, 2022
    Publication date: April 3, 2025
    Applicant: SHANGHAI OPHTHAL-BRIGHT BIOMEDICINE TECHNOLOGY
    Inventors: Shiqing ZHANG, Xiaojiang WU, Liping GU, Hong YU
  • Patent number: 12257208
    Abstract: A box for drug management and recycle is provided, which includes a drug box body, a camera device, a card-swiping device, a display device, a processor, and a power supply. A RFID detection device and electronic locks are arranged in the recycle box. A wireless communication module, an early warning module and a processing module are arranged in the processor, and the processor is wirelessly connected to a server terminal. The acquisition and return of the drugs can be jointly completed through face recognition and card-swiping recognition, and can be specified to an individual according to the obtained employee number and other information, thus facilitating the strict management of drug and achieving the recycle of unwanted drug. Therefore, the recycle box has a broad clinical prospect.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: March 25, 2025
    Inventors: Hong Yu, Xin Yu, Hongyuan Lv, Zihao Huang
  • Patent number: 12260730
    Abstract: Disclosed is a pair of visualization monitoring glasses, comprising a monocular. The monocular comprises a lens and a temple. The temple is internally provided with a chip, an optical display system, an interactive system, and an early warning system. The chip is configured to receive a monitoring signal, form a display signal according to the monitoring signal, and send the display signal out. The optical display system is configured to receive the display signal and display the display content through the lens. The interactive system is configured to acquire a gesture action and control the optical display system to switch different display content according to the gesture action. The early warning system is configured to acquire the monitoring signal, perform safety analysis according to the monitoring content, and control the optical display system to perform safety feedback.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: March 25, 2025
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Hong Yu, Xin Yu, Hongyuan Lv
  • Patent number: 12261215
    Abstract: A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 25, 2025
    Assignee: GlobalFoundaries U.S. Inc.
    Inventors: Hong Yu, Haiting Wang, Zhenyu Hu
  • Publication number: 20250089317
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with a bottom epitaxial semiconductor material and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets; a plurality of gate structures surrounding individual semiconductor nanosheets of the plurality of semiconductor nanosheets; a first semiconductor material of a first conductivity type at source/drain regions of the plurality of gate structures; and a second semiconductor material of a second conductivity type above the first semiconductor material, the first conductivity type being different than the second conductivity type.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Inventors: Hong YU, William J. TAYLOR, JR.
  • Publication number: 20250078304
    Abstract: An evaluation method of craniofacial asymmetry index based on artificial intelligence is disclosed and includes: a craniofacial image shooting step: obtaining a craniofacial model file of a patient; an artificial intelligence head shape identification and feature point marking step: importing the craniofacial model file into an artificial intelligence algorithm, performing identification and feature point marking on a craniofacial image in the craniofacial model file to generate at least one feature point; a craniofacial space coordinate axis establishment step: including a coordinate axis y-z plane establishment step, a coordinate axis origin establishment step and a z-axis orientation definition step; and an artificial intelligence skew degree estimation step: inputting the craniofacial model file and corresponding coordinate axes into an artificial intelligence skew degree evaluation algorithm simultaneously, and presenting a craniofacial skew degree in a data visualization manner.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 6, 2025
    Inventors: Pang-Yun Chou, Chang-Chun Lee, Sheng-Hong Yu, De-Yi Yeh
  • Publication number: 20250051547
    Abstract: Provided herein are antimicrobial polymer compositions and antimicrobial coating formulations useful for preparing antimicrobial substrates and imparting antimicrobial properties to surfaces, and methods for their use and preparation thereof.
    Type: Application
    Filed: January 28, 2023
    Publication date: February 13, 2025
    Inventors: Wenjun MENG, Shengchang TANG, Jihan YI, Mingyu ZHANG, Wai Hong YU, Sze Wing WONG
  • Patent number: 12213536
    Abstract: An electronic cigarette, comprising a shell and a power supply installed in the shell, and the electronic cigarette further comprises a tobacco bin which is provided in the shell and communicates with the outside air, and a suction nozzle which communicates with the tobacco bin; and a piezoelectric ceramic piece which clings to the tobacco bin is provided in the shell, the piezoelectric ceramic piece is a bearing surface of the tobacco bin on which a tobacco material is loaded as well as a heating surface of the tobacco bin, and the piezoelectric ceramic piece is electrically connected with the power supply. The electronic cigarette has a simple atomization mode and directly atomizes the tobacco material by means of the high frequency vibration and heat of the piezoelectric ceramic.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: February 4, 2025
    Assignee: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Jianfu Liu, Kejun Zhong, Xiaoyi Guo, Wei Huang, Yuangang Dai, Xinqiang Yin, Jianhua Yi, Hong Yu, Yang Wang
  • Publication number: 20250040237
    Abstract: An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: Vitor A. Vulcano Rossi, Anton V. Tokranov, Hong Yu, David C. Pritchard
  • Publication number: 20250040167
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate-all-around field effect transistors and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding the plurality of semiconductor nanosheets; a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures; an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: Navneet K. JAIN, Romain H. A. FEUILLETTE, David C. PRITCHARD, James P. MAZZA, Hong YU
  • Publication number: 20250031439
    Abstract: A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: Hong Yu, Navneet K. Jain, David Charles Pritchard, Romain H.A. Feuillette
  • Publication number: 20250029869
    Abstract: An isolation structure for a substrate is disclosed. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: Jianwei Peng, Hong Yu
  • Patent number: 12205949
    Abstract: Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.
    Type: Grant
    Filed: June 28, 2024
    Date of Patent: January 21, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Zhenyu Hu, Hong Yu, Haiting Wang
  • Publication number: 20250022763
    Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Hong-Yu Guo, Tsung-Shu Lin
  • Publication number: 20250022825
    Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.
    Type: Application
    Filed: November 15, 2023
    Publication date: January 16, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Hong-Yu Guo, Tsung-Shu Lin, Hsin-Yu Pan
  • Patent number: 12198714
    Abstract: The disclosure relates to a voice signal analysis method and device and a chip design method and device. The voice signal analysis method includes: in a first updating gradient, training a resolution recovery model by using first voice training data meeting a same grouping condition in multiple mission sets; in a second updating gradient, training the resolution recovery model by interleavingly using second voice training data meeting different grouping conditions in the mission sets; iteratively executing the first and second updating gradients to set an initial model parameter of the resolution recovery model; and recovering a high-resolution snore signal from a low-resolution snore signal by using the resolution recovery model. The low-resolution snore signal has a lower resolution than the high-resolution snore signal.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: January 14, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Liang-Hsuan Tai, Hong-Yu Chen, Yen-Ting Wu, Ting-Yu Wang
  • Publication number: 20240429237
    Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Anton TOKRANOV, Man GU, Eric Scott KOZARSKY, George MULFINGER, Hong YU