Abstract: The invention provides a light generating device (100) comprising (i) n filaments (200), (ii) an power distribution unit (400), and (iii) electronics (500); wherein: (a) each of the n filaments (200) comprises one or more solid state light sources (10), wherein n?1, wherein each of the n filaments (200) comprises at least m electrical contacts (221), wherein m?2; and wherein the n filaments (200) are configured to generate filament light (201); (b) the power distribution unit (400) comprises k electrically conductive tracks (410) separated by electrically insulating material (420), wherein k?2; (c) at least two of the electrical contacts (221) of the n filaments (200) are functionally coupled to at least two different electrically conductive tracks (410); (d) the at least two different electrically conductive tracks (410) are functionally coupled to the electronics (500); and (e) the electronics (500) comprise one or more of a control system, a driver, and a transformer.

Abstract: Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

Abstract: A network device generates one or more search keys to include information retrieved from one or more fields in a header of a packet being processed by the network device. The network device performs a first-stage search in a first-stage memory to map the one or more search keys to one or more search key identifiers. Respective ones of the one or more search key identifiers are shorter than corresponding ones of the one or more search keys. The network device also performs a second-stage search in a second-stage memory based on a combination of the one or more search key identifiers to identify an entry that matches the combination of the one or more search key identifiers. The entry indicates a processing rule matched by the packet. The network device performs, with respect to the packet, an action associated with the rule.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wraparound gate structure and methods of manufacture. The structure includes: a channel region comprising semiconductor material; an isolation structure surrounding the channel region; a divot within the isolation structure; and a gate structure comprising gate material within the divot and surrounding the channel region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

Abstract: A germ-repellent paper product contains a paper substrate and a germ-repellent overprint varnish. The germ-repellent overprint varnish contains a varnish and a germ-repellent agent. The germ-repellent overprint varnish is coated onto the paper substrate to form a germ-repellent paper product. A method for manufacturing such a germ-repellent paper product is also provided.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

Abstract: An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

Abstract: Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin.

Abstract: A depth completion method of sparse depth map includes: acquiring a grayscale image and a sparse depth map corresponding to the grayscale image; obtaining a nearest neighbor interpolation (NNI) image and a Euclidean distance transform (EDT) image based on the sparse depth map; inputting the grayscale image, the NNI image, and the EDT image into a neural network model, thereby outputting a predicted residual map; and generating a predicted dense depth map according to the predicted residual map and the NNI image.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

Abstract: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.

Abstract: A method for efficient disposal of dioxin and heavy metals based on calcium-based heat storage of MSWI fly ash is provided. According to the method, MSWI fly ash washed with water is treated with ammonia, and carbon dioxide is continuously introduced under stirring. The ammonia provides OH? for a carbonation reaction of the MSWI fly ash and promotes removal of sulfate ions. After centrifugation of a reaction solution, calcium carbonate obtained as a solid part is transported to a calcinator of a solar chemical heat reservoir and calcined into calcium oxide by means of solar energy obtained by a solar concentrator. CO2 produced in a calcination process is collected, cooled and liquefied, followed by a carbonation reaction with the calcium oxide in a carbonation radiator. After the operations above are repeated in cycles for several times, carbonated MSWI fly ash is obtained for use as an aggregate or a filler.

Abstract: An apparatus and method are described for graphics virtualization with late synchronization. For example, a virtualized graphics execution environment is implemented on a host, including a hypervisor to virtualize graphics processing resources for one or more virtual machines (VMs). A plurality of graphics commands are received responsive to execution of a graphics application in one of the VMs. The graphics commands are persisted until a frame triggering event is detected. Upon detection of a frame triggering event, the persisted graphics commands are submitted to the host.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate electrode, an isolation structure, and an electrode plate. The gate electrode is over the substrate and the isolation structure is in contact with the gate electrode. The electrode plate is in the isolation structure.

Abstract: An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.

Abstract: Systems and processes for operating a digital assistant are provided. An example process for performing a task includes, at an electronic device having one or more processors and memory, receiving a spoken input including a request, receiving an image input including a plurality of objects, selecting a reference resolution module of a plurality of reference resolution modules based on the request and the image input, determining, with the selected reference resolution module, whether the request references a first object of the plurality of objects based on at least the spoken input, and in accordance with a determination that the request references the first object of the plurality of objects, determining a response to the request including information about the first object.