Patents by Inventor Hongyong Zhang
Hongyong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7847355Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.Type: GrantFiled: August 3, 2009Date of Patent: December 7, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
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Patent number: 7838968Abstract: There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between ?5×109 and 5×109 dyn/cm2. This can suppress peeling of the interlayer dielectric films and difficulties in forming contact holes. Furthermore, release of hydrogen from the active layer can be suppressed. In this way, highly reliable TFTs can be obtained.Type: GrantFiled: December 5, 2005Date of Patent: November 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Satoshi Teramoto
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Patent number: 7821011Abstract: An LDD structure is manufactured to have a desired aspect ratio of the height to the width of a gate electrode. The gate electrode is first deposited on a semiconductor substrate followed by ion implantation with the gate electrode as a mask to form a pair of impurity regions. The gate electrode is then anodic oxidized to form an oxide film enclosing the electrode. With the oxide film as a mask, highly doped regions are formed by ion implantation in order to define lightly doped regions between the highly doped regions and the channel region located therebetween.Type: GrantFiled: November 25, 2008Date of Patent: October 26, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang
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Patent number: 7817232Abstract: A liquid crystal display apparatus containing an image sensor, which comprises a liquid crystal display part comprising an active matrix circuit, a peripheral driver circuit for driving the active matrix circuit, and a sensor part, integrated on one substrate, wherein the sensor part is sealed and protected with a sealing part and a counter substrate.Type: GrantFiled: April 15, 2009Date of Patent: October 19, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Masayuki Sakakura
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Patent number: 7800235Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.Type: GrantFiled: August 26, 2005Date of Patent: September 21, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang
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Patent number: 7791117Abstract: To fabricate an active matrix type display device integrated with an image sensor at a low cost and without complicating process, an image sensor laminated with TFT and a light receiving unit is formed on a light receiving matrix, a display matrix is arranged with TFT and pixel electrodes on a matrix and formed with an electrode layer functioning as a black matrix, a lower electrode of the light receiving unit is formed by a starting film the same as that of the black matrix, a terminal for fixing potential of an upper electrode is formed by starting films the same as those of a signal line, the electrode layer or pixel electrodes and the terminals function also as shield electrodes for a side face of the light receiving unit since potential thereof is fixed.Type: GrantFiled: August 14, 2007Date of Patent: September 7, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Masayuki Sakakura, Yurika Satou
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Patent number: 7786553Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.Type: GrantFiled: July 28, 1999Date of Patent: August 31, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang
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Patent number: 7781271Abstract: A process for laser processing an article which comprises: heating the intended article to be doped with an impurity to a temperature not higher than the melting point thereof said article being made from a material selected from a semiconductor a metal an insulator and a combination thereof; and irradiating a laser beam to the article in a reactive gas atmosphere containing said impurity thereby allowing the impurity to physically or chemically diffuse into combine with or intrude into said article.Type: GrantFiled: January 29, 2007Date of Patent: August 24, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 7749819Abstract: It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.Type: GrantFiled: June 6, 2007Date of Patent: July 6, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi
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Publication number: 20100157188Abstract: A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is concentrated on the laminated spacer portion, whereby destruction of a thin-film transistor of the peripheral driver circuits can be prevented caused by the pressure from the sealing portion.Type: ApplicationFiled: January 27, 2010Publication date: June 24, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hongyong Zhang, Satoshi Teramoto
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Patent number: 7723788Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon.Type: GrantFiled: February 11, 2009Date of Patent: May 25, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
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Publication number: 20100081247Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film an a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.Type: ApplicationFiled: October 15, 2009Publication date: April 1, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hongyong ZHANG, Hideki UOCHI, Toru TAKAYAMA, Takeshi FUKUNAGA, Yasuhiko TAKEMURA
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Patent number: 7687809Abstract: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion.Type: GrantFiled: May 2, 2008Date of Patent: March 30, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Hongyong Zhang
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Patent number: 7683978Abstract: A metal electrode also serving as a black matrix is so formed as to cover the periphery of an ITO pixel electrode. A region where the pixel electrode and the metal electrode coextend also serves as an auxiliary capacitor. Since the auxiliary capacitor can be formed by using a thin insulating film, it can have a large capacitance. By virtue of the structure in which the black matrix also serves as the auxiliary capacitor, it is not necessary to provide an electrode dedicated to the auxiliary capacitor, thereby preventing reduction in aperture ratio. Further, the black matrix can completely shield a source line and a gate line from light.Type: GrantFiled: March 12, 2007Date of Patent: March 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang
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Publication number: 20100068860Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.Type: ApplicationFiled: November 19, 2009Publication date: March 18, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hongyong ZHANG, Yasuhiko TAKEMURA, Toshimitsu KONUMA, Hideto OHNUMA, Naoaki YAMAGUCHI, Hideomi SUZAWA, Hideki UOCHI
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Publication number: 20100044714Abstract: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of the same material as the pixel electrode is disposed to form the auxiliary capacitor by utilizing the pixel electrode. It allows a required value of auxiliary capacitor to be obtained without dropping the aperture ratio. Also, it allows the electrode pattern to function as a electrically shielding film for suppressing the cross-talk between the source and gate lines and the pixel electrode.Type: ApplicationFiled: November 2, 2009Publication date: February 25, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hongyong Zhang, Satoshi Teramoto
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Patent number: 7667817Abstract: A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is concentrated on the laminated spacer portion, whereby destruction of a thin-film transistor of the peripheral driver circuits can be prevented caused by the pressure from the sealing portion.Type: GrantFiled: July 24, 2007Date of Patent: February 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Satoshi Teramoto
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Publication number: 20100041187Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon.Type: ApplicationFiled: October 23, 2009Publication date: February 18, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yasuhiko TAKEMURA, Hongyong ZHANG, Satoshi TERAMOTO
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Patent number: 7649227Abstract: An insulated gate semiconductor device comprising an insulator substrate having provided thereon a source and a drain region; a channel region being incorporated between said source and said drain regions, said channel region comprising a polycrystalline, a single crystal, or a semi-amorphous semiconductor material; and a region provided under said channel region, said region comprising an amorphous material containing the same material as that of the channel region as the principal component, or said region comprising a material having a band gap larger than said channel region. A process for fabricating the device is also disclosed.Type: GrantFiled: November 9, 2006Date of Patent: January 19, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang
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Patent number: RE41690Abstract: Method of processing, e.g., laser annealing, objects such as semiconductor devices with pulsed lasers with high production yield and high reproducibility so as to obtain good characteristics stably. The pulse width of the irradiated pulse beam is set to more than 30 nsec to stabilize the processing. To achieve a pulse width exceeding 30 nsec, plural lasers are connected in series or in parallel and excited successively.Type: GrantFiled: May 21, 2001Date of Patent: September 14, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang