Abstract: A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.

Abstract: An unlocking key for a port lock of an electronic device for unlocking and separating, from a port of the electronic device, a blocking module which is inserted and coupled to the port of the electronic device and has a key recess in which a pattern part and a latch key holding recess are formed on different inner surfaces of the key recess, includes a main body casing, a movable housing installed to protrude from a front end of the main body casing, a pattern key which is fixedly installed to protrude from a front end of the movable housing, a latch key which protrudes from the front end of the movable housing, and a manipulation part which is movably installed in the main body casing and controls reciprocating of the movable housing and opening and closing of the latch key.

Abstract: Disclosed are a redistribution layer structure, a method of forming a redistribution layer structure, a semiconductor package device including a redistribution layer structure, and a method of manufacturing a semiconductor package device including a redistribution layer structure. The semiconductor package device may include a redistribution layer structure, wherein the redistribution layer structure may include a first insulating layer having one or more openings open to a target region and an unetched portion configured to improve the flatness of the redistribution layer structure in the remaining region excluding the one or more openings in the space corresponding to the target region and a first wiring member layer disposed on the first insulating layer so as to at least partially fill the one or more openings.

Abstract: Disclosed are a chip bonding apparatus for semiconductor packaging and a semiconductor packaging method using the same. The chip bonding apparatus may include a bonding head, wherein the bonding head may include a plurality of chip holding units, each of which is configured to individually hold a chip, and the bonding head may be configured to adjust the interval between the plurality of chip holding units. The chip bonding apparatus may be configured to bond a plurality of chips to a given target surface at controlled intervals using the plurality of chip holding units according to a multi-chip bonding method. The semiconductor packaging method may include bonding chips to a target surface of a carrier substrate at controlled intervals using the plurality of chip holding units according to the multi-chip bonding method.

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

Abstract: A positive electrode for a lithium-sulfur battery, a positive electrode comprising the same, a lithium secondary battery comprising the positive electrode, and a method for preparing a positive electrode slurry are provided. The positive electrode comprises a positive electrode active material, a first conductive material and a second conductive material, wherein the positive electrode active material comprises a sulfur-carbon composite comprising a porous carbon material and sulfur (S), the first conductive material comprises fibers having an average particle size of 5 ?m or less and the second conductive material comprises secondary particles including agglomerates of two or more primary particles of carbon nanotubes (CNT), and the combination of the conductive materials provides improved output characteristics and capacity of the lithium secondary battery.

Abstract: A battery management system, a battery pack, an electric vehicle and a battery management method are provided. The BMS includes a sensing unit for detecting voltage, current, and pressure of the battery cell, a memory for storing first relationship data representing the relationship between OCV and SOC and second relationship data representing the relationship between pressure and SOC, and a control unit for determining a voltage value, a current value, and a pressure value, and determining a SOC estimation value of the battery cell at each set time. The control unit compares a previous SOC estimation value with a plateau section, and determines a current SOC estimation value by executing at least one of (i) a first SOC estimation value based on the voltage value, the current value and the first relationship data, and (ii) a second SOC estimation value based on the pressure value and the second relationship data.

Abstract: An electronic device is provided. The electronic device includes a first communication circuit, a second communication circuit, a processor configured to be electrically connected with the first communication circuit and the second communication circuit, and a memory configured to be electrically connected with the processor. The memory includes instructions, when executed by the processor, cause the processor to obtain location information of the electronic device, transmit a first message for requesting to change a state of the electronic device to a network, receive a first response message to the transmitted first message from the network, transmit a second message for requesting a parameter for an operation cycle of the second communication circuit to the network, receive a second response message to the second message from the network, and change the operation cycle of the second communication circuit to a value corresponding to a current state of the electronic device.

Abstract: A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

Abstract: A port blocking module of an electronic device and a port locking apparatus having the same includes a module frame which is formed to correspond to size and shape of a port of an electronic device, a locking module having a locking module body fixedly installed inside the module frame, a first locking member connected to the locking module body to be elastically transformable such that the first locking member selectively comes into contact with a terminal part inside the port, and a second locking member connected to the locking module body to be elastically transformable such that the second locking member is disposed by being spaced apart from the first locking member, and a pattern module which is installed to be movable between a locking position and an unlocking position inside and outside the module frame.

Abstract: An electrode assembly has a one or more first electrode plates, separators, and second electrode plates are stacked, wherein the first electrode plate include a first electrode tab portion, to which a first active material is not applied, on one side thereof in a width direction, and the first electrode tab portion extends further outward in the width direction from one side end portion of the electrode assembly in the width direction than the separator, and an insulating coating is formed on a slit surface of the second electrode plate, which is disposed adjacent to the first electrode tab portion with the separator interposed therebetween, at one side end portion of the electrode assembly. The insulating coating is formed after coating and slitting a second active material on the second electrode plate and before stacking the first electrode plate, the second electrode plate, and the separator.

Abstract: A battery control device includes: a connector turning ON or OFF a connection state between a plurality of batteries and an output terminal to which a discharge current is output, for each battery; a controller controlling the connector such that the plurality of batteries are connected in parallel with each other to the output terminal and discharged during a first discharge period from a start time of discharge of the plurality of batteries each of which SOC is a predetermined reference value or more until a time when the SOC of at least one of the plurality of batteries reaches the reference value, and connected alternatively to the output terminal and discharged during a second discharge period from a time when the SOC of each of the plurality of batteries becomes lower than the reference value until a time when the discharge of the plurality of batteries is terminated.

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

Abstract: A system for holding a first set of die during a first placement operation onto a substrate and placing a second set of additional die onto the same substrate during a second placement operation. The first set of die have a different height than the second set of die and the sets of die may comprise an entire wafer of die. A stretchable mounting film has an adhesive to which a set of die and a frame attach. The frame has an open center portion formed by two or more outer support rail sections that are expandable to an expanded position. An optional frame lock may secure the frame in the expanded position. The frame and mounting tape can be expanded along a first axis, a second axis, or both, which separates the die adhesively attached to the mounting film.

Abstract: Disclosed are an interconnection module substrate for a semiconductor package, a semiconductor package device including the same, and manufacturing methods thereof. The interconnection module substrate includes a plurality of via-defining structures disposed spaced apart from each other in a horizontal direction, each of the plurality of via-defining structures including a substrate material unit and a conductive via element extending through the substrate material unit in a vertical direction, at least one interconnection bridge member disposed spaced apart from or adjacent to the plurality of via-defining structures in the horizontal direction, and a substrate material layer embedded in the space between and around the plurality of via-defining structures and the interconnection bridge member to form a single substrate shape together therewith, the substrate material layer being configured to expose the plurality of via-defining structures and the interconnection bridge member.

Abstract: The present invention relates to a method for deriving cephalometric parameters for orthodontic diagnosis based on machine learning. More specifically, the present invention relates to a method for deriving cephalometric parameters for orthodontic diagnosis based on machine learning, wherein a machine-learning algorithm is applied after acquiring a 3D cone-beam computer tomography (CBCT) image of a subject data taken in a natural head position, and a plurality of cephalometric landmarks can be precisely and rapidly digitized on the 3D CBCT image in order to derive 13 diagnosis parameters for precise orthodontic diagnosis.

Abstract: Provided is a method for manufacturing an all-solid-state battery which allows a solid electrolyte layer and an electrode to be in sufficiently close in contact with each other without deformation of the electrode shape or damages upon the electrode. The method for manufacturing an all-solid-state battery includes applying slurry for a solid electrolyte layer to the surface of an electrode active material layer to form a patterned solid electrolyte layer, and carrying out pressurization to form a solid electrolyte layer.

Abstract: A system for holding multiple semiconductor die during a single placement operation onto a substrate. The system includes a stretchable mounting film having an adhesive to which two or more semiconductor die and a frame attaches. The frame has an open center portion formed by two or more outer support rail sections that are expandable to an expanded position. An optional frame lock may secure the frame in the expanded position. The frame may have four sections allowing expansion along two axis. The frame sections may have connection points configured to releasably attach the frame to a position control device that expands the sections to the expanded position. The frame and mounting tape can be expanded by stretching along a first axis, a second axis, or both, which separates the two or more dies adhesively attached to the mounting film while the dies are attached to the mounting film.

Abstract: A battery capacity recovery apparatus and a battery capacity recovery method are provided. The battery capacity recovery apparatus includes a sensing unit configured to measure voltage and current of a battery, and a control unit configured to determine an electric state of the battery based on time series data of each of the voltage and the current of the battery. When it is determined to execute the capacity recovery process based on the electric state of the battery, the control unit is configured to sequentially execute the first capacity recovery routine and the second capacity recovery routine. The first capacity recovery routine is a procedure that discharges the battery until a state of charge (SOC) of the battery decreases to a reference state of charge (SOC). The second capacity recovery routine is a procedure that rests the battery during a reference time or more from a completion time point of the first capacity recovery routine.