Abstract: An electrode assembly has a one or more first electrode plates, separators, and second electrode plates are stacked, wherein the first electrode plate include a first electrode tab portion, to which a first active material is not applied, on one side thereof in a width direction, and the first electrode tab portion extends further outward in the width direction from one side end portion of the electrode assembly in the width direction than the separator, and an insulating coating is formed on a slit surface of the second electrode plate, which is disposed adjacent to the first electrode tab portion with the separator interposed therebetween, at one side end portion of the electrode assembly. The insulating coating is formed after coating and slitting a second active material on the second electrode plate and before stacking the first electrode plate, the second electrode plate, and the separator.

Abstract: A battery control device includes: a connector turning ON or OFF a connection state between a plurality of batteries and an output terminal to which a discharge current is output, for each battery; a controller controlling the connector such that the plurality of batteries are connected in parallel with each other to the output terminal and discharged during a first discharge period from a start time of discharge of the plurality of batteries each of which SOC is a predetermined reference value or more until a time when the SOC of at least one of the plurality of batteries reaches the reference value, and connected alternatively to the output terminal and discharged during a second discharge period from a time when the SOC of each of the plurality of batteries becomes lower than the reference value until a time when the discharge of the plurality of batteries is terminated.

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

Abstract: A system for holding a first set of die during a first placement operation onto a substrate and placing a second set of additional die onto the same substrate during a second placement operation. The first set of die have a different height than the second set of die and the sets of die may comprise an entire wafer of die. A stretchable mounting film has an adhesive to which a set of die and a frame attach. The frame has an open center portion formed by two or more outer support rail sections that are expandable to an expanded position. An optional frame lock may secure the frame in the expanded position. The frame and mounting tape can be expanded along a first axis, a second axis, or both, which separates the die adhesively attached to the mounting film.

Abstract: Disclosed are an interconnection module substrate for a semiconductor package, a semiconductor package device including the same, and manufacturing methods thereof. The interconnection module substrate includes a plurality of via-defining structures disposed spaced apart from each other in a horizontal direction, each of the plurality of via-defining structures including a substrate material unit and a conductive via element extending through the substrate material unit in a vertical direction, at least one interconnection bridge member disposed spaced apart from or adjacent to the plurality of via-defining structures in the horizontal direction, and a substrate material layer embedded in the space between and around the plurality of via-defining structures and the interconnection bridge member to form a single substrate shape together therewith, the substrate material layer being configured to expose the plurality of via-defining structures and the interconnection bridge member.

Abstract: The present invention relates to a method for deriving cephalometric parameters for orthodontic diagnosis based on machine learning. More specifically, the present invention relates to a method for deriving cephalometric parameters for orthodontic diagnosis based on machine learning, wherein a machine-learning algorithm is applied after acquiring a 3D cone-beam computer tomography (CBCT) image of a subject data taken in a natural head position, and a plurality of cephalometric landmarks can be precisely and rapidly digitized on the 3D CBCT image in order to derive 13 diagnosis parameters for precise orthodontic diagnosis.

Abstract: Provided is a method for manufacturing an all-solid-state battery which allows a solid electrolyte layer and an electrode to be in sufficiently close in contact with each other without deformation of the electrode shape or damages upon the electrode. The method for manufacturing an all-solid-state battery includes applying slurry for a solid electrolyte layer to the surface of an electrode active material layer to form a patterned solid electrolyte layer, and carrying out pressurization to form a solid electrolyte layer.

Abstract: A battery capacity recovery apparatus and a battery capacity recovery method are provided. The battery capacity recovery apparatus includes a sensing unit configured to measure voltage and current of a battery, and a control unit configured to determine an electric state of the battery based on time series data of each of the voltage and the current of the battery. When it is determined to execute the capacity recovery process based on the electric state of the battery, the control unit is configured to sequentially execute the first capacity recovery routine and the second capacity recovery routine. The first capacity recovery routine is a procedure that discharges the battery until a state of charge (SOC) of the battery decreases to a reference state of charge (SOC). The second capacity recovery routine is a procedure that rests the battery during a reference time or more from a completion time point of the first capacity recovery routine.

Abstract: A system for holding multiple semiconductor die during a single placement operation onto a substrate. The system includes a stretchable mounting film having an adhesive to which two or more semiconductor die and a frame attaches. The frame has an open center portion formed by two or more outer support rail sections that are expandable to an expanded position. An optional frame lock may secure the frame in the expanded position. The frame may have four sections allowing expansion along two axis. The frame sections may have connection points configured to releasably attach the frame to a position control device that expands the sections to the expanded position. The frame and mounting tape can be expanded by stretching along a first axis, a second axis, or both, which separates the two or more dies adhesively attached to the mounting film while the dies are attached to the mounting film.

Abstract: Disclosed is a fan-out package in which two or more dies are integrated in a fan-out packaging process, wherein the fan-out package includes a bridge structure including a bridge substrate formed on one side of the fan-out package, a redistribution layer formed on the bridge substrate, the redistribution layer including at least one trace, the redistribution layer being configured to electrically connect the dies to each other, and a passive element formed in the redistribution layer by patterning. The routing density of the trace is relieved, and electrical performance is improved by the provision of the passive element.

Abstract: An apparatus provides information on a distance to empty (DTE) of a vehicle and an information providing method is performed thereby. The apparatus includes a display device configured to display DTE information of a vehicle and a controller configured to control operation of the display device. The controller determines low fuel efficiency-related information and high fuel efficiency-related information based on a current vehicle driving condition. The controller determines a low DTE value and a high DTE value based on the low fuel efficiency-related information, the high fuel efficiency-related information, and a current available battery energy. The controller also determines a current DTE value indicating a real-time DTE and controls operation of the display device to display the low DTE value, the high DTE value, and the current DTE value.

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

Abstract: A semiconductor device includes a via pattern in a first interlayer insulating film, and a wiring pattern that extends in a first direction and is on the first interlayer insulating film and the via pattern. The wiring pattern includes a lower wiring line and an upper wiring line on the lower wiring line, where the lower wiring line and the upper wiring line are stacked in a second direction, where the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern, where a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness, and where a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness.

Abstract: A lithium-sulfur battery having high energy density and a method for manufacturing the same are provided. The lithium-sulfur battery at depth of discharge (DOD) 15% to DOD 80% includes a compound having three or more characteristic peaks of diffraction angles (2? values) of X-ray diffraction (XRD) patterns selected from 7.1±0.2°, 9.0±0.2°, 9.4±0.2°, 9.6±0.2°, 9.9±0.2°, 10.0±0.2°, 10.4±0.2°, 11.0±0.2°, 11.6±0.2°, 12.1±0.2°, 13.3±0.2°, 14.5±0.2° and 15.0±0.2°.

Abstract: There is provided a cloud-based application programming interface (API) service providing system. The system may comprise a cloud management console issuing authentication information for a requested API among a plurality of APIs, an API manager receiving a call message for a specific API, which comprises authentication information, from a user's terminal, performing authentication using the authentication information in the call message, and requesting the execution of the specific API based on the authentication result and an API execution engine generating the result of executing the specific API in response to a request from the API manager, wherein the cloud management console is a module belonging to a control plane, and the call message is received by the API manager belonging to a data plane without via the control plane.

Abstract: A method for providing a cloud-based application programming interface (API) service is provided. The method may include issuing an authentication key corresponding to an application for some of a plurality of API services, performing authentication for a first user using the issued authentication key in response to a call for a first API service by the first user, and executing the first API service based on a result of the authentication.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a first dielectric layer including a first pad, a second dielectric layer on the first dielectric layer, a through electrode that penetrates the second dielectric layer and is electrically connected to the first pad, an upper passivation layer on the second dielectric layer, a second pad on the upper passivation layer, and an upper barrier layer between the upper passivation layer and the second pad. The first pad and the through electrode include a first material. The second pad includes a second material that is different from the first material of the first pad and the through electrode. The second pad includes a first part on the upper passivation layer, and a second part that extends from the first part into the upper passivation layer and is connected to the through electrode.

Abstract: Provided is a stack molding machine including an upper mold having formed therein a first runner and a first gate serving as a path of a resin material, a first intermediate plate provided under and combined with the upper mold, and having formed therein a first molding connected to the first gate to mold at least a portion on a first substrate placed under the first intermediate plate, a dummy plate provided under and spaced a certain distance apart from the first intermediate plate, a second intermediate plate provided under the dummy plate, and having formed therein a second molding connected to a second gate to mold at least a portion under a second substrate placed under the dummy plate, and a lower mold having formed therein a second runner and the second gate serving as a path of the resin material, and combined with the second intermediate plate.