Patents by Inventor Hoon Han

Hoon Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974433
    Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: April 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Heon Kang, Tae Hun Kim, Jae Ryong Sim, Kwang Young Jung, Gi Yong Chung, Jee Hoon Han, Doo Hee Hwang
  • Publication number: 20240132849
    Abstract: The present disclosure relates to a non-alcoholic fatty liver artificial tissue model. As compared to a conventional technology by which tissues are cultured only in Matrigel including a device composed of a decellularized liver tissue-derived extracellular matrix and a plurality of microchannels or a decellularized liver tissue-derived extracellular matrix, the present disclosure enables better mimicking of an actual non-alcoholic fatty liver disease due to the presence of Kupffer cells and hepatic stellate cells. Also, according to the present disclosure, the growth of liver organoids can be improved and fat accumulation and inflammation in the liver organoids can be caused to occur well through free fatty acid treatment, and the phenotypes of non-alcoholic fatty liver can be better expressed.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 25, 2024
    Inventors: Seung Woo CHO, Su Kyeom KIM, Baofang CUI, Jin KIM, Soo Han BAE, Dai Hoon HAN
  • Publication number: 20240125804
    Abstract: The present invention relates to a pharmaceutical composition for preventing or treating neurodegenerative diseases comprising a COX2 acetylating agent as an active ingredient and, more particularly, to a pharmaceutical composition for preventing or treating neurodegenerative diseases comprising, as an active ingredient, a COX2 acetylating agent which exhibits an effect of inhibiting the deposition of amyloid-? in brain neurons, reducing excessive neuroinflammatory responses, and increasing the phagocytosis of amyloid-? in microglial cells. The pharmaceutical composition for preventing or treating neurodegenerative diseases comprising the COX2 acetylating agent as an active ingredient has the effects of alleviating neuroinflammation by promoting COX2 acetylation in neurons and secreting specialized pro-resolving mediators (SPMs) and thus, can be very useful in the development of a preventive or therapeutic agent for neurodegenerative diseases.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: Jae-Sung BAE, Hee Kyung Jin, Ju Youn Lee, Seung Hoon Han
  • Publication number: 20240123291
    Abstract: An electronic device and/or a wearable device providing an exercise program, and/or a control method thereof are provided. The electronic device may include a communication module configured to communicate with the wearable device. The electronic device may include at least one processor. The processor may provide a first exercise program of a first exercise period according to an initial exercise intensity range to a user wearing the wearable device. The processor may measure a first posture score of the user while the user is performing the first exercise program. The processor may compare the first posture score to a posture boundary value. The processor may set a personal exercise intensity range of the user based on a result of the comparing. The processor may provide a second exercise program of a second exercise period according to the personal exercise intensity range.
    Type: Application
    Filed: October 31, 2023
    Publication date: April 18, 2024
    Inventors: Chiyoung AHN, Joayoung LEE, Harkjoon KIM, Seungjoon LEE, Hoon HAN
  • Patent number: 11963357
    Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kohji Kanamori, Seo-Goo Kang, Hyo Joon Ryu, Sang Youn Jo, Jee Hoon Han
  • Patent number: 11963358
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Joon Ryu, Young Hwan Son, Seo-Goo Kang, Jung Hoon Jun, Kohji Kanamori, Jee Hoon Han
  • Publication number: 20240114675
    Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Jung-Hoon Han, Je Min Park
  • Patent number: 11948882
    Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihoon Chang, Jimin Choi, Yeonjin Lee, Hyeon-Woo Jang, Jung-Hoon Han
  • Patent number: 11948808
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 2, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
  • Patent number: 11934735
    Abstract: A method and a device capable of supporting various display methods using an electronic device and/or glasses-type wearable electronic device (e.g., AR glasses) in an augmented reality (AR) are provided. An AR providing device for AR services includes a display and a processor. The processor is configured to provide content through an AR screen, detect a specified external object through the AR screen while providing the content, determine a display mode for providing the content, based on detection of the specified external object, control to display the content through a display of the specified external object, based on the determined display mode, and perform control to display the content through a virtual display area associated with the specified external object on the AR screen, based on the determined display mode.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: March 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngchan Woo, Donghee Kang, Choonkyoung Moon, Christian Park, Joayoung Lee, Jiwon Jeon, Hoon Han
  • Publication number: 20240084126
    Abstract: A graft copolymer, and a graft copolymer composition having excellent particulate dispersibility in a curable resin such as an epoxy resin and is applicable as a particulate impact reinforcing agent, a curable resin composition including same, and methods of preparing them.
    Type: Application
    Filed: August 12, 2022
    Publication date: March 14, 2024
    Applicant: LG Chem, Ltd.
    Inventors: Min Ah Jeong, Ki Hyun Yoo, Sang Hoon Han, Yong Kyun Kim
  • Publication number: 20240066717
    Abstract: A robot is provided. The robot includes a display, a memory storing identification information of the robot, a communication interface communicating with a server providing a virtual environment service, and at least one processor configured to, based on receiving a user input for interlocking the robot with the virtual environment service, transmit the identification information of the robot stored in the memory to the server through the communication interface, and based on receiving interaction information related to an avatar corresponding to the identification information of the robot from the server through the communication interface, control an operation of the robot based on the interaction information.
    Type: Application
    Filed: May 22, 2023
    Publication date: February 29, 2024
    Inventors: Yeeun CHOI, Hoon HAN, Jinah KONG, Hyojin KIM, Jiwoong HWANG, Seungjoon LEE
  • Publication number: 20240071810
    Abstract: Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device comprises forming a first layer which has a first surface, does not comprise an acid, and comprises a metal material; forming, on the first layer, a second layer which comprises a trench exposing the first surface, has a second surface intersecting the first surface within the trench, and comprises an acid and an organic material; providing a first precursor comprising an alkoxy group and silicon; and forming a third layer comprising silicon oxide on the second surface within the trench. The third layer is in contact with a portion of the first surface within the trench.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun Hyea KO, Hoon Han, Byung Keun Hwang, Young Hun Sung, Youn Joung Cho
  • Patent number: 11912804
    Abstract: A core-shell copolymer, a method of making the same, and a thermoplastic resin composition including the same are disclosed herein. In some embodiments, a core-shell copolymer includes a core and a shell surrounding the core, the core includes a conjugated diene-based monomer-derived repeating unit and a phosphate-based cross-linking agent-derived cross-linking part represented by Formula 1, and the shell includes a first alkyl (meth)acrylate monomer-derived repeating unit, a second alkyl (meth)acrylate monomer-derived repeating unit, and a sulfonate-based ionic monomer-derived repeating unit represented by Formula 2. The core is 68 parts to 92 parts and the shell is 8 parts to 32 parts, based on 100 parts of the core-shell copolymer, the core has a swell index of 2.7 to 10.9, the shell includes 1 wt % to 16 wt % of the sulfonate-based ionic monomer-derived repeating unit, and the shell has a weight average molecular weight of 105,000 g/mol to 645,000 g/mol.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: February 27, 2024
    Assignee: LG Chem, Ltd.
    Inventors: Kwang Jin Lee, Yoon Ho Kim, Sang Il Nam, Kyung Bok Sun, Chang No Lee, Sang Hoon Han
  • Publication number: 20240062808
    Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.
    Type: Application
    Filed: September 4, 2023
    Publication date: February 22, 2024
    Inventors: Kohji KANAMORI, Sang Youn JO, Jee Hoon HAN
  • Publication number: 20240063279
    Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Inventors: Doosan Back, Dongoh Kim, Gyuhyun Kil, Jung-Hoon Han
  • Patent number: 11910613
    Abstract: A semiconductor memory device includes a mold structure including a plurality of wordlines on a front side of a first substrate, and a string selection line and a stopper line on the plurality of wordlines. A channel structure extends in a vertical direction to penetrate the mold structure. A block separation area extends in a first direction to cut the mold structure. A protective structure is interposed between the block separation area and the stopper line and not between the block separation area and the string selection line and not between the block separation area and the plurality of wordlines. A string separation structure extends in the first direction to cut the string selection line and the stopper line. A bitline extends in a second direction on the mold structure. A bitline contact connects the channel structure and the bitline.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Joon Ryu, Hee Suk Kim, Jeong Yong Sung, Jee Hoon Han
  • Patent number: 11907690
    Abstract: Disclosed are an electronic terminal apparatus and an operating method thereof. The present invention relates to an electronic terminal apparatus equipped with a UI development tool, which is able to provide an automatic UI component creation function through an image analysis of a UI design plan, and an operating method thereof.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: February 20, 2024
    Assignee: TOBESOFT CO., LTD.
    Inventor: Jung Hoon Han
  • Publication number: 20240057336
    Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cuttin
    Type: Application
    Filed: October 23, 2023
    Publication date: February 15, 2024
    Inventors: Kohji Kanamori, Jee Hoon Han, Seo-Goo Kang, Hyo Joon Ryu
  • Patent number: 11899025
    Abstract: The present invention relates to a pharmaceutical composition for preventing or treating neurodegenerative diseases comprising a COX2 acetylating agent as an active ingredient and, more particularly, to a pharmaceutical composition for preventing or treating neurodegenerative diseases comprising, as an active ingredient, a COX2 acetylating agent which exhibits an effect of inhibiting the deposition of amyloid-? in brain neurons, reducing excessive neuroinflammatory responses, and increasing the phagocytosis of amyloid-? in microglial cells. The pharmaceutical composition for preventing or treating neurodegenerative diseases comprising the COX2 acetylating agent as an active ingredient has the effects of alleviating neuroinflammation by promoting COX2 acetylation in neurons and secreting specialized pro-resolving mediators (SPMs) and thus, can be very useful in the development of a preventive or therapeutic agent for neurodegenerative diseases.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 13, 2024
    Assignee: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Jae-Sung Bae, Hee Kyung Jin, Ju Youn Lee, Seung Hoon Han