Abstract: A method for manufacturing a CZTS based thin film having a dual band gap slope, comprising the steps of: forming a Cu2ZnSnS4 thin film layer; forming a Cu2ZnSn(S,Se)4 thin film layer; and forming a Cu2ZnSnS4 thin film layer. A method for manufacturing a CZTS based solar cell having a dual band gap slope according to another aspect of the present invention comprises the steps of: forming a back contact; and forming a CZTS based thin film layer on the back contact by the method described above.

Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.

Abstract: Provided is an iron-based amorphous alloy and a method of manufacturing the same. More particularly, provided is an high carbon iron-based amorphous alloy expressed by a general formula Fe?C?Si?BxPyCrz, wherein ?, ?, ?, x, y and z are atomic % of iron (Fe), carbon (C), silicon (Si), boron (B), phosphorus (P), and chrome (Cr) respectively, wherein ? is expressed by ?=100?(?+?+x+y+z) atomic %, ? is expressed by 13.5 atomic %???17.8 atomic %, ? is expressed by 0.30 atomic %???1.50 atomic %, x is expressed by 0.1 atomic %?x?4.0 atomic %, y is expressed by 0.8 atomic %?y?7.7 atomic %, and z is expressed by 0.1 atomic %?z?3.0 atomic %.

Abstract: A display device includes: a first substrate; a second substrate disposed opposite to the first substrate; a first electrode and a second electrode disposed on the first substrate; a third electrode and a fourth electrode disposed on the second substrate; and a liquid crystal layer injected between the first substrate and the second substrate and including a plurality of liquid crystal molecules, where the second electrode extends substantially in a first direction, the third electrode extends substantially in a second direction, and the first direction and the second direction are perpendicular to each other.

Abstract: A 3D display apparatus is provided, which includes a display panel which displays a multi-viewpoint image, a barrier arranged on one side of the display panel unit, and a controller which controls the barrier to alternately form light transmitting areas and light blocking areas. The barrier includes a liquid crystal layer, a plurality of upper electrodes arranged to be spaced apart from one another on an upper surface of the liquid crystal layer, and a plurality of lower electrodes arranged to be spaced apart from one another on a lower surface of the liquid crystal layer.

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof, which can easily increase the number of input/output pads by increasing regions for forming the input/output pads such that a redistribution layer is formed to extend up to an encapsulant.

Abstract: Disclosed is a multi-layered composite panel. The multi-layered composite panel comprises at least two sheets of thin plates with continuous waveform patterns having the same pitch and different heights in one direction are overlapped. In the multi-layered composite panel, an air layer is formed between the overlapping thin plates, orthogonal pressing portions, which divide the waveform patterns on the top and the bottom of the thin plates into the unit of triangle-patterned cell by being pressed orthogonally to cross each other on the top and the bottom of the thin plates overlapping in the orthogonal direction crossing the direction of the waveform patterns, are formed and an undercut portion is formed by pressing the centers of both sides connecting a groove and a ridge of each cell on the top and the bottom of the thin plates with opposite orthogonal pressing portions.

Abstract: A display apparatus is provided. The display apparatus includes a display panel comprising a plurality of pixels including a plurality of sub-pixels, and arranges and displays a multi-view image in an arrangement pattern. The display panel includes a polarizing film disposed on a back surface of the display panel and which transmits, to the display panel, light having a first polarization direction to an area corresponding to a first part of each of the sub-pixels, and light having a second polarization direction to an area corresponding to a second part of the sub-pixels. a polarizing panel disposed on a back surface of the polarizing film and configured to adjusts the first and second polarization directions of the light transmitted by the polarizing film, and a controller configured to control a driving state of the polarizing panel to sequentially provide the first and second polarization directions for one image frame section.

Abstract: Solder compositions for semiconductor fabrication are provided that include silver (Ag) of 3.0 wt. % to 4.0 wt. %, copper (Cu) of 0.75 wt. % to 1.0 wt. %, nickel (Ni) of 0.08 wt. % to 1.0 wt. %, and tin (Sn) of 94 wt. % to 96.17 wt. %, or that include bismuth (Bi) of 0.3 wt. % to 2.0 wt. % in place of a portion of the tin (Sn) in the solder composition; and, semiconductor packages are also provided that use the solder compositions for bonding one or more components of the semiconductor packages to each other.

Abstract: Disclosed herein is a device for controlling a sample temperature during photoelectric measurement of the sample. The device for controlling a sample temperature during photoelectric measurement of the sample includes: a sample stage to which a measurement target sample is fixed; a cooling unit for cooling the sample by injecting air; and a temperature measuring unit having a thermometer that measures a temperature of the sample. The device has an effect of easily controlling the temperature of a measurement target sample by employing a direct control method for a sample temperature, in which air or cooled air is injected to the sample.

Abstract: The present invention relates to a microstrip circuit and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a microstrip circuit. The microstrip circuit includes a feeding line providing a signal, a probe being connected to one end of the feeding line, and a patch emitting the signal to a waveguide. The patch is disposed in a layer opposite to a layer in which the feeding line and the probe are disposed, with a core substrate being positioned therebetween. At least one of length of the probe, thickness of the core substrate, and permittivity of the core substrate is determined based on bandwidth of a transition between the microstrip circuit and the waveguide.

Abstract: Disclosed is a method of forming a CIGS-based thin film having high efficiency using a simple process at relatively low temperatures. The method includes an Ag thin film forming step and an ACIGS forming step of depositing Cu, In, Ga, and Se on the surface of the Ag thin film using a vacuum co-evaporation process. Ag, constituting the Ag thin film, is completely diffused, while Cu, In, Ga, and Se are deposited to form ACIGS together with Cu, In, Ga, and Se co-evaporated in a vacuum during the ACIGS forming step. The Ag thin film is formed and CIGS elements are then deposited using vacuum co-evaporation to form an ACIGS thin film having improved power generation efficiency at a relatively low temperature of 400° C. or less using only a single-stage vacuum co-evaporation process.

Abstract: A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.

Abstract: A method of fabricating an Ag—(Cu—)In—Ga—Se (A(C)IGS) based thin film using Se—Ag2Se core-shell nanoparticles, an A(C)IGS based thin film fabricated by the method, and a tandem solar cell having the A(C)IGS thin film are disclosed. More particularly, a method of fabricating a densified Ag—(Cu—)In—Ga—Se (A(C)IGS) based thin film by non-vacuum coating a substrate with a slurry containing Se—Ag2Se core-shell nanoparticles, an A(C)IGS based thin film fabricated by the method, and a tandem solar cell including the A(C)IGS based thin film are disclosed. According to the present invention, an A(C)IGS based thin film including Ag is manufactured by applying Se—Ag2Se core-shell nanoparticles in a process of manufacturing a (C)IGS thin film, thereby providing an A(C)IGS based thin film having a wide band gap.

Abstract: A 3D image display apparatus includes a display panel configured to display a multiview image, a light guide plate disposed in a rear of the display panel and spaced apart from the display panel, a main pattern repeatedly formed and spaced at a preset interval, and a light source configured to irradiate light to the light guide plate. A height of a sub pattern disposed in a light incident portion of the light guide plate near the light source among sub patterns constituting the main pattern is smaller than that of a sub pattern disposed in a central portion of the light guide plate.

Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.

Abstract: Disclosed are a modified conjugated diene polymer and a method for preparing the same. The modified conjugated diene polymer and the method for preparing the same advantageously provide superior compatibility with an inorganic filler, heat generation, tensile strength and abrasion resistance, low fuel consumption and excellent resistance on wet roads.