Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

Abstract: Vertical 3D cross point memory has memory cells formed at cross points of vertical bit lines and horizontal word lines. The memory cells are formed of two layers, enabling higher density than conventional techniques. One of the layers optionally includes OTS (Ovonic Threshold Switch) material to enable information storage.

Abstract: The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.

Abstract: A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a memory element, a spacer structure, and an upper element structure. The memory element includes a lower memory layer and an upper memory layer on the lower memory layer. The spacer structure is on a sidewall surface of the lower memory layer. The upper element structure is electrically connected on the upper memory layer. A recess is defined by a lower surface of the upper element structure, an upper surface of the lower memory layer and a sidewall surface of the upper memory layer.

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.

Abstract: A method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of output values in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.

Abstract: A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

Abstract: A memory cell formed in a pillar structure between a first electrode and a second electrode includes laminated encapsulation structure. In one example, the pillar includes a body of ovonic threshold switch material, carbon-based intermediate layers, metal layers and a body of phase change memory material in electrical series between the first and second electrodes. The laminated encapsulation structure surrounds the pillar. The laminated dielectric encapsulation structure comprises at least three conformal layers, including a first layer of material, a second conformal layer of a second layer material different from the first layer material; and a third conformal layer of a third layer material different from the second layer material.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

Abstract: An inductor structure and a manufacturing method for the same are provided. The inductor structure includes conductive layers and conductive elements. The conductive layers overlap in a vertical direction. Each of the conductive elements is coupled between two conductive layers of the conductive layers.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Abstract: A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.