Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a stack of conductive strips and an opening through the stack exposing sidewalls of conductive strips on first and second sides of the opening. Some of the conductive strips in the stack are configured as word lines. Data storage structures are disposed on the sidewalls of the stack. A vertical channel film is disposed vertically in contact with the data storage structures. The vertical channel film is connected at a proximal end to an upper channel pad over the stack, and at a distal end to a lower channel pad disposed in a lower level of the opening. The upper and lower channel pads may comprise an epitaxial semiconductor and be thicker than the vertical channel film disposed on the sidewalls of the stack.

Abstract: A method for manufacturing a memory device comprises forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stack of conductive strips in amounts effective to result in a majority of the initial silicide layer being a mono-silicon silicide of the precursor metal. The method comprises depositing and annealing additional silicon material over the initial silicide layer in amounts effective to result in formation of di-silicon silicide of the precursor metal to form a landing pad on the top surface of the stack of conductive strips, the formation of the di-silicon silicide of the precursor metal consuming mono-silicon silicide of the initial silicide layer so a majority of a silicide of the landing pad is di-silicon silicide.

Abstract: A memory device includes a stack of conductive strips in a plurality of first levels with a first opening and a conductive strip in the second level with a second opening, both openings exposing sidewalls. Data storage structures are formed on the sidewalls of the conductive strips in the plurality of first levels. A first vertical channel structure including vertical channel films is disposed in the first opening, the vertical channel films in contact with the data storage structures. The second opening is aligned with the first vertical channel structure. A gate dielectric layer is disposed on the sidewall of the conductive strip in the second level. A second vertical channel structure including vertical channel films is disposed in the second opening in contact with the gate dielectric layer on the sidewall of the conductive strip in the second level.

Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a stack of conductive strips and an opening through the stack exposing sidewalls of conductive strips on first and second sides of the opening. Some of the conductive strips in the stack are configured as word lines. Data storage structures are disposed on the sidewalls of the stack. A vertical channel film is disposed vertically in contact with the data storage structures. The vertical channel film is connected at a proximal end to an upper channel pad over the stack, and at a distal end to a lower channel pad disposed in a lower level of the opening. The upper and lower channel pads may comprise an epitaxial semiconductor and be thicker than the vertical channel film disposed on the sidewalls of the stack.

Abstract: A voltage sensitive switching device has a first electrode, a second electrode, and a switching layer between the first and second electrodes, comprising a tellurium free, low germanium composition of arsenic As, selenium Se and germanium Ge. The switching device is used in 3D cross-point memory.

Abstract: A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers.

Abstract: A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers.

Abstract: A voltage sensitive switching device is described having a superlattice-like cell structure comprising layers of ovonic materials, such as chalcogenide alloys. Memory cells can include the switching device, such as can be utilized in a cross-point memory.

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

Abstract: A 3D memory device includes a substrate, a multi-layers stack, at least one memory structure and an etching stop structure. The substrate has a trench. The multi-layers stack includes a first extending portion forming a non-straight angle with a bottom surface of the trench and a second extending portion, wherein both of the first extending portion and the second extending portion include a plurality of conductive layers and a plurality of insulating layers alternatively stacked in the trench. The memory structure is formed in the first extending portion. The etching stop structure is at least partially disposed in the second extending portion and has a material identical to that of the memory structure.

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

Abstract: An integrated circuit includes a memory array including a plurality of memory cells disposed at respective cross points of a plurality of first access lines and a plurality of second access lines. A selected memory cell has a first threshold voltage Vth(S) of set state and a second threshold voltage Vth(R) of reset state. Control circuitry is configured to apply a write voltage Vw to the selected first access line during a write operation, to apply a read voltage Vr to the selected first access line during a read operation, and to apply a same inhibit voltage Vu to unselected first and second access lines during the write and read operations, where ½Vw>Vu>Vw?Vth(S).

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided. A multi-layered stack is formed above a substrate, and the multi-layered stack comprises a plurality of nitride layers and polysilicon layers arranged alternately. Several channel holes are formed vertically to the substrate. The multi-layered stack is patterned to form linear spaces between the channel holes, wherein the linear spaces extend downwardly for being vertical to the substrate and to expose sidewalls of the nitride layers and the polysilicon layers. Then, the polysilicon layers are replaced with insulating layers having air-gaps through the linear spaces, and the nitride layers are replaced with conductive layers through the linear spaces.

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening.

Abstract: A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.

Abstract: A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.

Abstract: Phase change memory materials in a dielectric-doped, antimony-rich GST family of materials which are antimony rich relative to GST-225, are described that have speed, retention and endurance characteristics suitable for storage class data storage A memory device includes an array of memory cells, where each memory cell includes a first electrode and a second electrode coupled to a memory element. The memory element comprises a body of phase change memory material that comprises a combination of Ge, Sb, and Te with a dielectric additive in amounts effective to provide a crystallization transition temperature greater than to 160° C., greater that 170° C. in some effective examples and greater than 190° C. in other effective examples. A controller is coupled to the array, and configured to execute set operations and reset operations for memory cells in the array.

Abstract: A 3D memory device includes a plurality of vertical pillars composed of a vertical channel and a multilayer data storage structure. The multilayer data storage structure can comprise a dielectric charge trapping structure. A stack of dielectric lined conductive strips separated in the stack by insulating strips have sidewalls disposed adjacent the corresponding vertical pillars. The conductive strips have a dielectric liner having a dielectric constant ? greater than 7 on the sidewalls in contact with the outside layer of the multilayer data storage structure on the corresponding pillar. The conductive strips in embodiments described herein can comprise a relatively low resistance material, such as a metal or a metal nitride. A manufacturing method using Si—Ge selective etching of sacrificial layers can be used in a gate replacement process to form the dielectric conductive strips.