Patents by Inventor Hsiang Wang

Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12204357
    Abstract: The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yi-Hsiang Wang
  • Patent number: 12188682
    Abstract: An evaporative-cooling window fan is configured to draw air from outdoors to indoors such that it is cooled and filtered as it passes there-through.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: January 7, 2025
    Inventors: Chi Hsiang Wang, Hao Han Wang
  • Patent number: 12192664
    Abstract: An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: January 7, 2025
    Assignee: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Yu-Hsiang Wang
  • Publication number: 20240428722
    Abstract: A light-emitting-diode driver structure applicable to driving a display panel and operation method thereof are provided. The LED driver structure includes at least one LED driving group, and the LED driving group is composed of a plurality of LED driving circuits which are serially connected in cascade. Each LED driving circuit of the LED driving group receives a data input signal in common. Upon receiving control signals, output signals are generated to drive the display panel. The multi-point driving circuit scheme can be fully or partially applied in the driver structure as required. In addition, a plurality of enable signals can be further adopted to activate each LED driving circuit, for avoiding the FIFO register used in the prior arts. By employing the disclosed technical contents, the present invention is effective in reducing both redundant power waste and circuit layout area of a conventional LED driver.
    Type: Application
    Filed: September 14, 2023
    Publication date: December 26, 2024
    Inventors: CHE-WEI YEH, YU-HSIANG WANG, HO-CHUN CHANG, PO-HSIANG FANG
  • Patent number: 12158039
    Abstract: An adapting sleeve has a main body segment, a rod passage, a tightening recess, and an abutting wall segment. The main body segment is adapted to be mounted in a tube segment of a fence door. The rod passage is formed through the main body segment for connecting a width adjusting rod of the fence door. The tightening recess is formed on an outer surface of the main body segment for connecting a tightening unit of the fence door. The abutting wall segment is located between the tightening recess and the rod passage. A thickness of the abutting wall segment is larger than a gap between the width adjusting rod and an inner surface of the rod passage. A material hardness of the abutting wall segment is lower than that of the width adjusting rod. The tightening unit abuts the width adjusting rod via the abutting wall segment.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 3, 2024
    Assignee: DEMBY DEVELOPMENT CO., LTD.
    Inventor: Tsung-Hsiang Wang
  • Publication number: 20240395481
    Abstract: A keycap includes a keycap main body and multiple metal oxides. The metal oxides are doped in the keycap main body and forms an opaque region and a light-transmitting region in the keycap main body. The light-transmitting region is formed by irradiating a portion of the opaque region with an energy beam. A transmittancy of the light-transmitting region is greater than a transmittancy of the opaque region. A manufacturing method of the keycap is also disclosed.
    Type: Application
    Filed: September 26, 2023
    Publication date: November 28, 2024
    Applicant: Chicony Electronics Co., Ltd.
    Inventors: Ching-Wu Yang, Pai-Hsiang Wang
  • Publication number: 20240396538
    Abstract: An integrated circuit includes a first conducting line and a second conducting line in a first metal layer above a first transistor and a second transistor. The first conducting line and the second conducting line, which are parallel and adjacent to each other, form a metal-insulator-metal capacitor. Each of the first transistor and the second transistor forms a metal-insulator-semiconductor capacitor. The circuit also includes a third conducting line connected to a source and a drain of the first transistor and configured to receive a first reference voltage. The circuit still includes a fourth conducting line connected to a source and a drain of the second transistor and configured to receive a second reference voltage.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yi-Hsiang WANG, Wei-Lin LAI
  • Publication number: 20240395846
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements. The solid-state image sensor also includes a color filter layer disposed above the photoelectric conversion elements and the color filter layer includes a first color filter layer. The first color filter layer has a central region, a peripheral region adjacent to the central region, and a corner region diagonally arranged from the central region. The solid-state image sensor further includes a meta structure disposed on the color filter layer. The meta structure includes pillars. The pillars that correspond to the central region, the peripheral region, and the corner region have different arrangements.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Inventors: Kai-Hao CHANG, Po-Hsiang WANG, Yu-Chi CHANG
  • Publication number: 20240395741
    Abstract: A semiconductor device and method including depositing a passivation layer over an upper contact feature. In some embodiments, a polyimide (PI) layer is formed over the passivation layer. In an example, the PI layer is patterned to form a patterned PI layer including a first opening that exposes a portion of the passivation layer over the upper contact feature. In an embodiment, one or more etching processes are performed to form a second opening that exposes a top surface of the upper contact feature. In some embodiments, the one or more etching processes etches the passivation layer through the first opening to form a patterned passivation layer. In some examples, the one or more etching processes also recesses sidewall surfaces of the patterned PI layer from corners of the patterned passivation layer defined along opposing surfaces of the second opening.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Inventors: Chung-Hao SU, Wen-Chiung TU, Hsing-Hsiang WANG, Chen-Chiu HUANG, Hsiang-Ku SHEN, Dian-Hau CHEN
  • Patent number: 12154885
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: November 26, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Shih-An Liao, Ying-Yang Su, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Publication number: 20240387172
    Abstract: A coating system and a method for using such a system comprising a vessel, a flexible container within the vessel, and a coating apparatus. The flexible container includes an outlet port, wherein the flexible container is configured to contract in response to an increase in pressure within the vessel. The flexible container is configured to output a coating composition through the outlet port in response to contraction. The coating apparatus is configured to receive the coating composition from the outlet port and in some embodiments, deliver the coating composition to a wafer surface.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chun-Ming CHEN, Chien-Liang LIN, Chun-Hsiang WANG, Jen-Yu TSAI
  • Publication number: 20240387719
    Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
  • Patent number: 12147811
    Abstract: A warp scheduling method includes: storing multiple first warps issued to a streaming multiprocessor in an instruction buffer module; marking multiple second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling a load/store unit stall cycle in each time interval to obtain a load/store unit stall cycle proportion; comparing the load/store unit stall cycle proportion with a stall cycle threshold value, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; and issuing the second warps from the instruction buffer module to a processing module for execution.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 19, 2024
    Inventors: Chung-ho Chen, Chien-ming Chiu, Yu-hsiang Wang
  • Patent number: 12148587
    Abstract: A manufacture method of a concave disc-shaped structure of bimetal strip, particularly to one that is a coaxial positioning method of the guide hole which having elastic disc-shape structure bimetal strips not affected by external stress, which having a bimetal structure which outer edge will not be damaged and does not affect by stress while inner edge pulling closed to the outer edge, it includes: a bimetal strip, a lug, and an assembling jig, having two displaceable positioning holes, and use the guiding surface to make the two positioning holes gradually turn inside to condense to the combining surface of the lugs, so as to achieve the purpose of accurate positioning and combination.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 19, 2024
    Inventors: Yi-Hsiang Wang, I-Ying Wang
  • Publication number: 20240381561
    Abstract: An expansion card frame assembly is configured to support a riser card and an expansion card. The expansion card frame assembly includes a frame, a pivotable component and a stopper. The frame is configured to support the riser card, and the expansion card is configured to be inserted into the riser card. The pivotable component is pivotably disposed on the frame and configured to be located aside the expansion card. The stopper is movably disposed on the pivotable component and configured to be located at one side of the expansion card which is located farther away from the riser card.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 14, 2024
    Inventors: CHENG-YAO TSAI, Wei Chen Lin, PING SHENG YEH, YEN-HSIANG WANG, YI-SHEN CHEN
  • Publication number: 20240379330
    Abstract: The present disclosure relates to an integrated chip processing tool. The integrated chip processing tool includes a gas distribution ring configured to extend along a perimeter of a process chamber. The gas distribution ring includes a lower ring extending around the process chamber. The lower ring has a plurality of gas inlets arranged along a bottom surface of the lower ring and a plurality of gas conveyance channels arranged along an upper surface of the lower ring directly over the plurality of gas inlets. The gas distribution ring further includes an upper ring disposed on the upper surface of the lower ring and covering the plurality of gas conveyance channels. A plurality of gas outlets are arranged along opposing ends of the plurality of gas conveyance channels. A plurality of gas conveyance paths extending between the plurality of gas inlets and the plurality of gas outlets have approximately equal lengths.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Po-Hsiang Wang, Min-Chang Ching, Kuo Liang Lu, Bo-Han Chu
  • Patent number: 12142245
    Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: November 12, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu, Yi-Yang Tsai, Po-Hsiang Fang
  • Patent number: 12142190
    Abstract: A display control system for controlling a display panel having a plurality of display zones includes a main controller, a plurality of display driver circuits and a plurality of memories. Each of the display driver circuits is coupled to a corresponding display zone among the plurality of display zones, to control the corresponding display zone. Each of the memories is coupled to a corresponding display driver circuit among the plurality of display driver circuits, to store a compensation data for the corresponding display zone controlled by the corresponding display driver circuit. The plurality of display driver circuits are cascaded through a plurality of first transmission channels and connected through at least one second transmission channel, and each of the first transmission channels is coupled between two of the plurality of display driver circuits or between one of the plurality of display driver circuits and the main controller.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: November 12, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chieh-An Lin, Chun-Wei Kang, Po-Hsiang Fang, Keko-Chun Liang, Jhih-Siou Cheng, Nien-Tsung Hsueh, Che-Wei Yeh, Yu-Hsiang Wang
  • Publication number: 20240359341
    Abstract: A modular gripper is disclosed and includes a main fixing plate, a driving module, two screw rods, two extension plates, two extension screws and two nuts. The two screw rods are arranged concentrically in the first direction, connected to the driving module, and driven by the driving module to rotate. The two extension plates are detachably docked to two sides of the main fixing plate through connection elements. The two extension screws are connected to the two screw rods, respectively. Threads of the two extension screws are continuously connected with threads of the two screw rods. The two nuts are sleeved on the two screw rods, respectively. When the two screw rods and the two extension screws are driven by the driving module to rotate synchronously, the two nuts are allowed to displace relative to the two screw rods and the two extension screws, to achieve a clamping operation.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 31, 2024
    Inventors: Hsin-Hua Chen, Tsao-Hsiang Wang
  • Patent number: D1053155
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 3, 2024
    Inventors: Yi-Hsiang Wang, I-Ying Wang