Patents by Inventor Hsiang Wang

Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395481
    Abstract: A keycap includes a keycap main body and multiple metal oxides. The metal oxides are doped in the keycap main body and forms an opaque region and a light-transmitting region in the keycap main body. The light-transmitting region is formed by irradiating a portion of the opaque region with an energy beam. A transmittancy of the light-transmitting region is greater than a transmittancy of the opaque region. A manufacturing method of the keycap is also disclosed.
    Type: Application
    Filed: September 26, 2023
    Publication date: November 28, 2024
    Applicant: Chicony Electronics Co., Ltd.
    Inventors: Ching-Wu Yang, Pai-Hsiang Wang
  • Publication number: 20240396538
    Abstract: An integrated circuit includes a first conducting line and a second conducting line in a first metal layer above a first transistor and a second transistor. The first conducting line and the second conducting line, which are parallel and adjacent to each other, form a metal-insulator-metal capacitor. Each of the first transistor and the second transistor forms a metal-insulator-semiconductor capacitor. The circuit also includes a third conducting line connected to a source and a drain of the first transistor and configured to receive a first reference voltage. The circuit still includes a fourth conducting line connected to a source and a drain of the second transistor and configured to receive a second reference voltage.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yi-Hsiang WANG, Wei-Lin LAI
  • Publication number: 20240395846
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements. The solid-state image sensor also includes a color filter layer disposed above the photoelectric conversion elements and the color filter layer includes a first color filter layer. The first color filter layer has a central region, a peripheral region adjacent to the central region, and a corner region diagonally arranged from the central region. The solid-state image sensor further includes a meta structure disposed on the color filter layer. The meta structure includes pillars. The pillars that correspond to the central region, the peripheral region, and the corner region have different arrangements.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Inventors: Kai-Hao CHANG, Po-Hsiang WANG, Yu-Chi CHANG
  • Patent number: 12154885
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: November 26, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Shih-An Liao, Ying-Yang Su, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Publication number: 20240387719
    Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
  • Publication number: 20240387172
    Abstract: A coating system and a method for using such a system comprising a vessel, a flexible container within the vessel, and a coating apparatus. The flexible container includes an outlet port, wherein the flexible container is configured to contract in response to an increase in pressure within the vessel. The flexible container is configured to output a coating composition through the outlet port in response to contraction. The coating apparatus is configured to receive the coating composition from the outlet port and in some embodiments, deliver the coating composition to a wafer surface.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chun-Ming CHEN, Chien-Liang LIN, Chun-Hsiang WANG, Jen-Yu TSAI
  • Patent number: 12148587
    Abstract: A manufacture method of a concave disc-shaped structure of bimetal strip, particularly to one that is a coaxial positioning method of the guide hole which having elastic disc-shape structure bimetal strips not affected by external stress, which having a bimetal structure which outer edge will not be damaged and does not affect by stress while inner edge pulling closed to the outer edge, it includes: a bimetal strip, a lug, and an assembling jig, having two displaceable positioning holes, and use the guiding surface to make the two positioning holes gradually turn inside to condense to the combining surface of the lugs, so as to achieve the purpose of accurate positioning and combination.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 19, 2024
    Inventors: Yi-Hsiang Wang, I-Ying Wang
  • Patent number: 12147811
    Abstract: A warp scheduling method includes: storing multiple first warps issued to a streaming multiprocessor in an instruction buffer module; marking multiple second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling a load/store unit stall cycle in each time interval to obtain a load/store unit stall cycle proportion; comparing the load/store unit stall cycle proportion with a stall cycle threshold value, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; and issuing the second warps from the instruction buffer module to a processing module for execution.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 19, 2024
    Inventors: Chung-ho Chen, Chien-ming Chiu, Yu-hsiang Wang
  • Publication number: 20240379330
    Abstract: The present disclosure relates to an integrated chip processing tool. The integrated chip processing tool includes a gas distribution ring configured to extend along a perimeter of a process chamber. The gas distribution ring includes a lower ring extending around the process chamber. The lower ring has a plurality of gas inlets arranged along a bottom surface of the lower ring and a plurality of gas conveyance channels arranged along an upper surface of the lower ring directly over the plurality of gas inlets. The gas distribution ring further includes an upper ring disposed on the upper surface of the lower ring and covering the plurality of gas conveyance channels. A plurality of gas outlets are arranged along opposing ends of the plurality of gas conveyance channels. A plurality of gas conveyance paths extending between the plurality of gas inlets and the plurality of gas outlets have approximately equal lengths.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Po-Hsiang Wang, Min-Chang Ching, Kuo Liang Lu, Bo-Han Chu
  • Publication number: 20240381561
    Abstract: An expansion card frame assembly is configured to support a riser card and an expansion card. The expansion card frame assembly includes a frame, a pivotable component and a stopper. The frame is configured to support the riser card, and the expansion card is configured to be inserted into the riser card. The pivotable component is pivotably disposed on the frame and configured to be located aside the expansion card. The stopper is movably disposed on the pivotable component and configured to be located at one side of the expansion card which is located farther away from the riser card.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 14, 2024
    Inventors: CHENG-YAO TSAI, Wei Chen Lin, PING SHENG YEH, YEN-HSIANG WANG, YI-SHEN CHEN
  • Patent number: 12142245
    Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: November 12, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu, Yi-Yang Tsai, Po-Hsiang Fang
  • Patent number: 12142190
    Abstract: A display control system for controlling a display panel having a plurality of display zones includes a main controller, a plurality of display driver circuits and a plurality of memories. Each of the display driver circuits is coupled to a corresponding display zone among the plurality of display zones, to control the corresponding display zone. Each of the memories is coupled to a corresponding display driver circuit among the plurality of display driver circuits, to store a compensation data for the corresponding display zone controlled by the corresponding display driver circuit. The plurality of display driver circuits are cascaded through a plurality of first transmission channels and connected through at least one second transmission channel, and each of the first transmission channels is coupled between two of the plurality of display driver circuits or between one of the plurality of display driver circuits and the main controller.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: November 12, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chieh-An Lin, Chun-Wei Kang, Po-Hsiang Fang, Keko-Chun Liang, Jhih-Siou Cheng, Nien-Tsung Hsueh, Che-Wei Yeh, Yu-Hsiang Wang
  • Publication number: 20240363151
    Abstract: The present invention provides a storage device suitable for high temperature. A plurality of memory devices are disposed on the top of a substrate, respectively, and connected electrically to a control device and a temperature sensor. The temperature sensor includes a first predetermined temperature, a second predetermined temperature, and a third predetermined temperature. The temperature sensor is used for sensing the temperature of the plurality of memory devices and generating a temperature value. The control device adjusts the transmission rate of the storage signal to make the storage device adapt to high temperature environments.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 31, 2024
    Inventors: CHIN FENG CHANG, Hsun Chia Ma, Wei Hsiang Wang
  • Publication number: 20240359341
    Abstract: A modular gripper is disclosed and includes a main fixing plate, a driving module, two screw rods, two extension plates, two extension screws and two nuts. The two screw rods are arranged concentrically in the first direction, connected to the driving module, and driven by the driving module to rotate. The two extension plates are detachably docked to two sides of the main fixing plate through connection elements. The two extension screws are connected to the two screw rods, respectively. Threads of the two extension screws are continuously connected with threads of the two screw rods. The two nuts are sleeved on the two screw rods, respectively. When the two screw rods and the two extension screws are driven by the driving module to rotate synchronously, the two nuts are allowed to displace relative to the two screw rods and the two extension screws, to achieve a clamping operation.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 31, 2024
    Inventors: Hsin-Hua Chen, Tsao-Hsiang Wang
  • Publication number: 20240355711
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen
  • Publication number: 20240355761
    Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor substrate includes a semiconductor material over a base substrate. The semiconductor substrate has one or more sidewalls forming a crack stop trench that is laterally between a central region of the semiconductor substrate and a peripheral region of the semiconductor substrate that surrounds the central region. The peripheral region of the semiconductor substrate includes a plurality of cracks.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
  • Patent number: 12125366
    Abstract: A system for physical-distancing detection in a specified area includes a locator locating a positioning quadrangle plane in a specified area; an image-capturing device obliquely capturing an image of the specified area to generate a captured image of the specified area; and a coordinate converter defining a coordinate conversion function according to raw coordinates of selected points of the positioning quadrangle plane in the captured image of the specified area and reference coordinates of the selected points of the positioning quadrangle plane in an overlooked image of the specified area. The image-capturing device converts raw coordinates of the captured image of the specified area into converted coordinates of the overlooked image of the specified area by way of the coordinate conversion function, determines a physical-distancing condition between two persons according to the converted coordinates, and automatically takes an action corresponding to the physical-distancing condition.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 22, 2024
    Assignee: ALPHA NETWORKS INC.
    Inventor: Cheng-Hsiang Wang
  • Publication number: 20240341061
    Abstract: A charging device includes a liquid cooled cable, a charging gun, a charging station, a station connector and a communicating pipe. The liquid cooled cable has a gun end and a station end. The liquid cooled cable includes a first insulating tube, a second insulating tube, a tape, a filler and a sheath. The first insulating tube has a first channel. The second insulating tube has a second channel and a braided copper mesh. The charging gun is connected to the gun end of the liquid cooled cable. The charging gun includes a gun connector and a first liquid return channel. The station connector includes a second liquid return channel and a connection part. One end of the second liquid return channel communicates to the second channel. The connection part is connected to the station end of the liquid cooled cable.
    Type: Application
    Filed: May 9, 2023
    Publication date: October 10, 2024
    Inventors: Ko-Ming CHEN, Duan-Yih LIN, Cheng-Hong CHEN, Shih-Wei WANG, Shih-Hsiang WANG
  • Patent number: 12111715
    Abstract: The present invention provides a memory structure, which is disposed on a first circuit board and connected electrically to a system power supply of a second circuit board. The memory structure comprises a plurality of memory unit, a power control component, and a display component. The power control component receives a first voltage of the system power supply. The power control component includes a power management unit and a linear voltage stabilizing unit. The display component includes a light-emitting unit and a control unit. The power control component provides a second voltage to the plurality of memory units using the power management unit. The linear voltage stabilizing unit provides a third voltage to the light-emitting unit and the control unit. The power management unit distributes the power supply to the plurality of memory units, the light-emitting unit, and the control unit for further usage.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: October 8, 2024
    Assignee: TEAM GROUP INC.
    Inventors: Yu Hsuan Yen, Hsi Lin Kuo, Wei Hsiang Wang, Chin Feng Chang
  • Publication number: 20240332411
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang