Abstract: A dummy load for automotive LED lights is revealed. The dummy load includes an automotive battery and a control module which is electrically connected both a body computer and a LED light module and provided with a LED control circuit and a charge control circuit. The charge control circuit includes a signal mixer circuit receiving signals from the body computer and discharge signals of the automotive battery, a charger integrated circuit (IC) and a feedback control circuit for battery both electrically connected to the signal mixer circuit, and a battery charging circuit electrically connected to the charger IC and transmitting charge signals to the feedback control circuit for battery and the automotive battery. Thereby a conventional dummy load resistor is replaced by the automotive battery for protecting the automotive LED light from overheating, increasing product stability and recycling a part of electricity for recharge of the automotive battery.

Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

Abstract: A light emitting apparatus, including: a first light emitting device with a first substrate having a first upper surface and first bottom surface, a plurality of first LED chips disposed on the first upper surface, emitting a light penetrating the first substrate, and a first wavelength conversion layer directly contacting the plurality of first LED chips and first upper surface, and a first shape in a cross-sectional view; a second wavelength conversion layer directly contacting the first bottom surface; a second shape in the cross-sectional view substantially the same as the first shape; a second light emitting device separated from the first light emitting device, including a second substrate and plurality of second LEDs disposed on the second substrate; a support base connected to the first light emitting device by a first angle and connected to the second light emitting device by a second angle; and a first support arranged between the support base and first light emitting device.

Abstract: A method of manufacturing an integrated circuit (IC) device includes forming a metal oxide semiconductor (MOS) transistor including a first gate and first and second source/drain (S/D) regions, the first and second S/D regions having a first doping type and being formed in a substrate region having a second doping type different from the first doping type, forming a guard ring structure surrounding the MOS transistor, the guard ring structure including a second gate and first and second heavily doped regions, the first and second heavily doped regions being formed in the substrate region and having the second doping type, and constructing a first electrical connection between the first and second gates.

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

Abstract: An adapting sleeve has a main body segment, a rod passage, a tightening recess, and an abutting wall segment. The main body segment is adapted to be mounted in a tube segment of a fence door. The rod passage is formed through the main body segment for connecting a width adjusting rod of the fence door. The tightening recess is formed on an outer surface of the main body segment for connecting a tightening unit of the fence door. The abutting wall segment is located between the tightening recess and the rod passage. A thickness of the abutting wall segment is larger than a gap between the width adjusting rod and an inner surface of the rod passage. A material hardness of the abutting wall segment is lower than that of the width adjusting rod. The tightening unit abuts the width adjusting rod via the abutting wall segment.

Abstract: A testing device is disclosed. The testing device includes a socket configured to support a DUT and a first detection module disposed at a first side of the socket and configured to detect a location relationship between the DUT and the socket.

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

Abstract: Provided is a food forming apparatus. An even speed device with a plurality of penetrating holes is disposed before the dough passes through the food shaping mold, making the dough to have even speed in the forming area (usually be cylindrical but not limited), then the food formed by passing through the food shaping mold Will have more consistent length and eliminate the technical issue about the inconsistent lengths of the food.

Abstract: The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.

Abstract: An atmospheric turbulence detection method includes: providing a temperature difference measuring device including a thermocouple element and two sensing probes, wherein the thermocouple element has two opposite end portions, the two sensing probes are respectively disposed at the two end portions, and there is an ambient distance between the two end portions; placing the temperature difference measuring device in an atmospheric environment to generate an electromotive force by a temperature difference between the two end portions; analyzing the electromotive force to convert the electromotive force into an ambient temperature difference of an environment where the two end portions of the thermocouple element are located, an atmospheric refractive index structure constant is calculated according to the ambient temperature difference and the ambient distance, and a value of the atmospheric refractive index structure constant corresponds to an ambient disturbance of an atmospheric turbulence.

Abstract: The disclosure provides a data receiver, including a first capacitor, a second capacitor, a first inverter and a second inverter. The first capacitor has a first terminal and a second terminal, and the first terminal receives a first input signal. The second capacitor has a third terminal and a fourth terminal, and the third terminal receives a second input signal. The first inverter has a first input terminal and a first output terminal. The second inverter has a second input terminal and a second output terminal. The first input terminal and the second output terminal are coupled to the second terminal of the first capacitor, and the second input terminal and the first output terminal are coupled to the fourth terminal of the second capacitor. The first output terminal generates a first output signal with a first output voltage, and the second output terminal generates a second output signal with a second output voltage.

Abstract: The electronic device includes a substrate; an active layer disposed above the first substrate; a first signal line disposed above the substrate; and a conductive pattern. The conductive pattern is in electrical contact with the active layer, wherein the conductive pattern includes a first side extending in a first direction, a second side extending in the first direction, and a third side connected between the first side and the second side, and wherein the third side includes a part that the part is not parallel to the first direction and not perpendicular to the first direction, and the part is located out of the first signal line.

Abstract: A curved panel includes a first curved substrate, a second curved substrate, a curved coverlens, and an adhesive structure. The first curved substrate and the second curved substrate are overlapped with each other. First to fourth sidewalls of the first curved substrate correspond to fifth to eighth sidewalls of the second curved substrate, respectively. The first to third sidewalls of the first curved substrate extend beyond the fifth to seventh sidewalls of the second curved substrate, respectively. The second curved substrate is located between the curved coverlens and the first curved substrate. The second curved substrate is bonded to the curved coverlens through an adhesive layer. The adhesive structure is located between the first curved substrate and the curved coverlens and is laterally located between the first sidewall and the fifth sidewall, between the second sidewall and the sixth sidewall, and between the third sidewall and the seventh sidewall.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of source contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate. The plurality of gate structures wrap around one or more of the plurality of source contacts in one or more closed loops. A drain contact is disposed over the substrate. The drain contact continuously wraps around one or more of the plurality of gate structures as a continuous structure. The plurality of gate structures are separated from the drain contact by a first distance and are separated from a source contact of the plurality of source contacts by a second distance. The second distance is different than the first distance.

Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.

Abstract: A thin film transistor substrate includes a substrate, a first conductive element and a semiconductor. The first conductive element is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The semiconductor is disposed on the substrate. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. In a top view, a virtual extending line disposes between the trace portion and the protrusive portion, the virtual extending line overlaps the second edge. At least a part of the semiconductor extends beyond the virtual extending line along a second direction vertical to the first direction.