Abstract: The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.

Abstract: An optical device includes a photoelectric conversion layer, an underlying layer, an anti-reflection layer, and a plurality of meta units. The underlying layer is disposed on the photoelectric conversion layer. The anti-reflection layer is disposed on the underlying layer. The meta units are disposed above the photoelectric conversion layer, in which each of the meta units includes a top portion and a bottom portion, and a projection of the bottom portion on the photoelectric conversion layer is within a projection of the top portion on the photoelectric conversion layer.

Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.

Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: An electronic device includes a substrate, a signal line, a semiconductor, a first conductive portion and a second conductive portion. The signal line is disposed on the substrate. The semiconductor is disposed on the substrate and overlapped with the signal line. Wherein the semiconductor is electrically connected to the first conductive portion and the second conductive portion. Wherein in a top view, at least a portion of the signal line is disposed between the first conductive portion and the second conductive portion. Wherein the first conductive portion has a first curve edge, the second conductive portion has a second curve edge, and the first curve edge and the second curve edge are facing the at least a portion of the signal line and are convex toward the at least a portion of the signal line.

Abstract: A semiconductor device includes a substrate, a buffer layer, a gradient layer, an active layer, a window layer, and an optical filtering layer. The substrate includes a first element and a second element. The buffer layer is disposed on the substrate. The gradient layer is formed on the buffer layer, and includes sublayers. Each sublayer includes the first, second, and third elements. For each sublayer, a lattice constant thereof is adjusted by changing a ratio of the second element to the third element. The active layer is formed on the gradient layer, and includes the first, second, and third elements. The window layer is formed on the active layer. The optical filtering layer includes the first, second, and third elements, and is formed on the window layer to block a portion of light having a wavelength in a predetermined wavelength range.

Abstract: The electronic device includes a substrate; an active layer disposed above the first substrate; a first signal line disposed above the substrate and overlapped with the active layer; and a conductive pattern disposed above the substrate. The conductive pattern includes a first side extending in a first direction, a second side extending in the first direction, and a third side connected between the first side and the second side, and wherein the third side includes a part that the part is not parallel to the first direction and not perpendicular to the first direction, and the part is located out of the first signal line and overlapped with the active layer.

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.

Abstract: An evaporative-cooling window fan is configured to draw air from outdoors to indoors such that it is cooled and filtered as it passes there-through.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

Abstract: A monitoring method of tracking and recognizing based on thermal images is executed by a monitoring system. The monitoring system includes a monitoring host and a monitoring server. The monitoring host is installed in a ward room, a bathroom, a workplace, or an operation place that needs monitoring. The monitoring host utilizes an infrared camera to capture thermal image frames of care recipients, and utilizes a trained AI human detection model to analyze the thermal image frames for recognizing a motion of a human in the thermal image frames. When the motion matches a condition for generating a warning signal, the monitoring host generates and transmits the warning signal to the monitoring server. Therefore, a care provider can determine whether the care recipients have unexpected behaviors, such as falling from a bed, falling, or staying still for a long time, and can deal with it immediately.

Abstract: A testing device is disclosed. The testing device includes a socket configured to support a DUT and a first detection module disposed at a first side of the socket and configured to detect a location relationship between the DUT and the socket.

Abstract: A wireless communication system includes a receiving apparatus and a transmitting apparatus. The transmitting apparatus includes a transmitting processing unit, configured to determine a wireless transmission channel on a first frequency band when in a first mode; a transmitting antenna unit, configured to transmit information of the wireless transmission channel and a channel state information of the wireless transmission channel on a second frequency band when in the first mode of the transmitting apparatus; and a wireless sensing unit, configured to perform a wireless sensing on the wireless transmission channel when in a second mode of the transmitting apparatus.

Abstract: The present invention provides a memory structure, which is disposed on a first circuit board and connected electrically to a system power supply of a second circuit board. The memory structure comprises a plurality of memory unit, a power control component, and a display component. The power control component receives a first voltage of the system power supply. The power control component includes a power management unit and a linear voltage stabilizing unit. The display component includes a light-emitting unit and a control unit. The power control component provides a second voltage to the plurality of memory units using the power management unit. The linear voltage stabilizing unit provides a third voltage to the light-emitting unit and the control unit. The power management unit distributes the power supply to the plurality of memory units, the light-emitting unit, and the control unit for further usage.

Abstract: A thin film transistor substrate includes a substrate, a first conductive element and a semiconductor. The first conductive element is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The semiconductor is disposed on the substrate. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. In a top view, a virtual extending line disposes between the trace portion and the protrusive portion, the virtual extending line overlaps the second edge. At least a part of the semiconductor extends beyond the virtual extending line along a second direction vertical to the first direction.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A computer vision vehicle locating fusion method includes: receiving an instant driving image from a camera, extracting multiple image features from the instant driving image and the multiple image features being extracted with the pre-stored feature sets in the storage device to fuse an inertial measurement parameter and the pre-stored satellite locating coordinate corresponding to one of the pre-stored feature sets that best matches the instant driving image to generate a first candidate coordinate; using the one satellite measurement coordinate received from a satellite locating device as a second candidate coordinate; calculating a first difference between the first candidate coordinate and an estimated reference coordinate, and calculating a second difference between the second candidate coordinate and the estimated reference coordinate; and determining and outputting the first candidate coordinate or the second candidate coordinate that has the smaller difference with the estimated reference coordinate.

Abstract: An optical device includes a photoelectric conversion layer, an anti-reflection layer, an underlying layer, a bottom meta layer, and a top meta layer. The photoelectric conversion layer includes a plurality of photodiodes. The anti-reflection layer is disposed on the photoelectric conversion layer. The underlying layer is disposed on the anti-reflection layer. The bottom meta layer is disposed on the underlying layer and includes a plurality of bottom meta units and a filling between the bottom meta units, in which the filling is continuously extend from the underlying layer, and a material of the filling is the same as a material of the underlying layer. The top meta layer is disposed above the bottom meta layer and includes a plurality of top meta units and a plurality of air recesses, in which the plurality of air recesses are respectively disposed between two adjacent top meta units.