Patents by Inventor Hsin-Hsien Wu

Hsin-Hsien Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140252380
    Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.
    Type: Application
    Filed: March 10, 2013
    Publication date: September 11, 2014
    Applicant: TSMC Solid State Lighting Ltd.
    Inventors: Ming-Shing Lee, Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming-Hua Lo, Chu-Ching Tsai
  • Publication number: 20140239323
    Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Inventors: Chyi Shyuan Chern, Hsin-Hsien wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Publication number: 20140235053
    Abstract: A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.
    Type: Application
    Filed: May 1, 2014
    Publication date: August 21, 2014
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chun-Lin Chang, Hsing-Kuo Hsia, Hung-Yi Kuo
  • Publication number: 20140217358
    Abstract: This application discloses a light-emitting diode comprising a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a semiconductor contact layer on the second semiconductor layer. The second semiconductor layer comprises a first sub-layer and a second sub-layer formed above the first sub-layer, wherein the material of the second sub-layer comprises AlxGa1-xN(0<x<1) and the second sub-layer has a surface comprising a structure of irregularly distributed holes.
    Type: Application
    Filed: January 23, 2014
    Publication date: August 7, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Yu-Yao LIN, Tsun-Kai KO, Chien-Yuan TSENG, Yen-Chih CHEN, Chun-Ta YU, Shih-Chun LING, Cheng-Hsiung YEN, Hsin-Hsien WU
  • Publication number: 20140174240
    Abstract: An apparatus for driving a SCARA robot is provided. The apparatus includes a body, a horizontal rotating arm, a linear motor coil and a vertical magnetic axis. The linear motor coil is disposed on the horizontal rotating arm, and the vertical magnetic axis is passed through the linear motor coil. Wherein, the vertical magnetic axis can be driven by the linear motor coil of the horizontal rotating arm by a non-contact magnetic force.
    Type: Application
    Filed: October 31, 2013
    Publication date: June 26, 2014
    Applicant: Delta Robot Automatic Co., Ltd.
    Inventors: Chih-Cheng PENG, Tsao-Hsiang WANG, Hsin-Hsien WU
  • Publication number: 20140167097
    Abstract: A method of fabricating an optoelectronic device comprising, providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a semiconductor epitaxial stack on the first major surface including a first conductive-type semiconductor layer having a first doping concentration, an active layer, and a second conductive-type semiconductor layer wherein the semiconductor epitaxial stack having four boundaries and a geometric center; and forming a plurality of the hollow components in the first conductive-type semiconductor layer wherein the plurality of the hollow components is formed from the boundary of the semiconductor epitaxial stack to the geometric center of the semiconductor epitaxial stack.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: HSIN-HSIEN WU, YU-YAO LIN, YEN-CHIH CHEN, CHIEN-YUAN TSENG, CHUN-TA YU, CHENG-HSIUNG YEN, SHIH-CHUN LING, TSUN-KAI KO, DE-SHAN KUO
  • Patent number: 8729525
    Abstract: The present application relates to an opto-electronic device. The opto-electronic device includes an n-cladding layer, a p-cladding layer and a multi-quantum well structure. The multi-quantum well structure is located between the p-cladding layer and the n-cladding layer, and includes a plurality of barrier layers, a plurality of well layers and a barrier tuning layer. The barrier tuning layer is made by doping the barrier layer adjacent to the p-cladding layer with an impurity therein for changing an energy barrier thereof to improve the light extraction efficiency of the opto-electronic device.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: May 20, 2014
    Assignee: Epistar Corporation
    Inventors: Jui-Yi Chu, Cheng-Ta Kuo, Yu-Pin Hsu, Chun-Kai Wang, Hsin-Hsien Wu, Yi-Chieh Lin
  • Patent number: 8722436
    Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 13, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 8716128
    Abstract: A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: May 6, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chun-Lin Chang, Hsing-Kuo Hsia, Hung-Yi Kuo
  • Publication number: 20140117306
    Abstract: A light-emitting device comprises a first type semiconductor layer, a multi-quantum well structure on the first type semiconductor layer, and a second type semiconductor layer on the multi-quantum well structure, wherein the multi-quantum well structure comprises a first portion near the first type semiconductor layer, a second portion near the second type semiconductor layer, and a strain releasing layer between the first portion and the second portion and comprising a first layer including Indium, a second layer including Aluminum on the first layer, and a third layer including Indium on the second layer, wherein the Indium concentration of the third layer is higher than that of the first layer.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: YU-YAO LIN, Yen-Chih Chen, Chien-Yuan Tseng, Tsun-Kai Ko, Chun-Ta Yu, Shih-Chun Ling, Cheng-Hsiung Yen, Hsin-Hsien Wu
  • Patent number: 8704252
    Abstract: This invention discloses a light-emitting device comprising a semiconductor stack layer having an active layer of a multiple quantum well (MQW) structure comprising alternate stack layers of quantum well layers and barrier layers, wherein the barrier layers comprise at least one doped barrier layer and one undoped barrier layer. The doped barrier layer can improve the carrier mobility of the electron holes and increase the light-emitting area and the internal quantum efficiency of the active layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 22, 2014
    Assignee: Epistar Corporation
    Inventors: Chun-Kai Wang, Schang-Jing Hon, Yu-Pin Hsu, Jui-Yi Chu, Hsin-Hsien Wu, Wei-Yu Yen
  • Publication number: 20140093990
    Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 3, 2014
    Applicant: TSMC Solid State Lighting Ltd.
    Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Ming Shing Lee, Huai-En Lai, Fu-Wen Liu, Andy Wu
  • Publication number: 20140065741
    Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 6, 2014
    Applicant: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 8624461
    Abstract: A motor stator includes an insulating frame having a plurality of projecting rods, an induction unit, and a plurality of conductive members. The induction unit includes an induction circuit board, a plurality of induction coils embedded within the induction circuit board, and a plurality of coil windings wound respectively on the projecting rods. The conductive members extend through the insulating frame and the induction circuit board for establishing an electrical connection between each of the induction coils and a corresponding one of the coil windings. The turn numbers of the coil windings are not limited by the area and thickness of the induction circuit board, and can be increased. Alternatively, the coil windings may be positioned to increase the magnetic pole slot number when energized. As such, a driving force of the motor stator can be increased.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: January 7, 2014
    Assignee: Yen Sun Technology Corp.
    Inventors: Chien-Jung Chen, Hsien-Wen Liu, Chih-Tsung Hsu, Tzu-Wen Tsai, Cheng-Tien Shih, Hsin-Hsien Wu, Jia-Ching Lee
  • Patent number: 8609446
    Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 17, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 8610161
    Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: December 17, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Ming Shing Lee, Huai-En Lai, Fu-Wen Liu, Andy Wu
  • Publication number: 20130330938
    Abstract: A method for forming a layer of material on a semiconductor wafer using a semiconductor furnace that includes a thermal reaction chamber having a heating system having a plurality of rotatable heaters for providing a heating zone with uniform temperature profile is provided. The method minimizes temperature variations within the thermal reaction chamber and promotes uniform thickness of the film deposited on the wafers.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zin-Chang WEI, Hsin-Hsien WU, Chun-Lin CHANG
  • Publication number: 20130260484
    Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: TSMC Solid State Lighting, Ltd.
    Inventors: Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Hsin Yang, Ching-Hua Chiu
  • Patent number: 8536491
    Abstract: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zin-Chang Wei, Hsin-Hsien Wu, Chun-Lin Chang
  • Publication number: 20130142720
    Abstract: This invention declares the method of preparation of cerium oxide supported palladium-gold catalysts and the process of destruction of volatile organic compounds in air to remove volatile organic compounds using the above catalysts. Destruction of volatile organic compounds in air stream over these catalysts is carried out in a fixed bed reactor to remove volatile organic compounds in air.
    Type: Application
    Filed: April 11, 2012
    Publication date: June 6, 2013
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL CENTRAL UNIVERSITY
    Inventors: Yu-Wen Chen, Hsien-Chang Yang, Hsin-Hsien Wu