Abstract: A method of chip sorting comprises providing a chip holder having a first surface; providing multiple chips on the first surface; providing a chip receiver having a second surface, wherein the second surface faces the first surface; attaching the multiple chips to the second surface; decreasing an adhesion between the multiple chips and the first surface; and separating the multiple chips from the first surface after the step of decreasing the adhesion between the multiple chips and the first surface.

Abstract: A method for developing multi-tenant application, a data accessing method of multi-tenant application and a system using the same are provided. The system includes a multi-tenant application manager, a storage unit, a business schema maintainer and a data entity maintainer. The multi-tenant application manager stores a multi-tenant application. The storage unit stores a metadata table and a data storage table. The business schema maintainer generates a table schema and a data accessing interface according to a business schema. The data entity maintainer performs a table updating operation on a tenant table schema in the metadata table of the storage unit according to the table schema. In addition, the multi-tenant application performs an accessing operation on the data storage table of the storage unit through the data accessing interface and the data entity maintainer.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: A chip sorting apparatus comprising a chip holder comprising a first surface and an second surface opposite to the first surface; a wafer comprising a first chip disposed on a first position of the first surface; a first chip receiver comprising a third surface and an fourth surface opposite to the third surface, wherein the third surface is opposite to the first surface; a pressurization device making the first chip and the third surface of the first chip receiver adhered to each other through pressuring the second surface at where corresponding to the first position; and a separator decreasing the adhesion between the first chip and the first surface.

Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Abstract: An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

Abstract: An air conditioning apparatus for use in information/data centers is provided, including a housing assembly, a wind-blowing device, a heat exchanger, and a separating mechanism. The housing assembly has a first housing and a second housing. The wind-blowing device is disposed in the housing assembly for guiding airflow into the housing assembly for heat exchange. The separating mechanism is used for dismembering the housing assembly in order to move the first housing or the second housing, and for incorporating the housing assembly to enable the heat exchanger to exchange heat.

Abstract: The present invention relates to a far-end control method with a security mechanism including a host transmitting an identification code through the PSTN (Public switched telephone network) to the I/O control device of the far-end. The I/O control device has a CPU to receive the identification code and judge whether the identification code matches with the predetermined value stored therein; if the identification code matches with the predetermined value, the mobile internet connection between the host and the I/O control device is activated to enable the host to mutually transmit information or signals with a far-end control device from the I/O control device through the mobile internet, and the connection will be disabled after the information or signal transmission is completed.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: An electrophoretic display panel includes a driving substrate and an electrophoretic display substrate. The driving substrate includes a first base material, driving electrode patterns, conductive lines, and a shielding layer. The first base material has a first configuration region and a second configuration region. The driving electrode patterns are located inside the first configuration region. The conductive lines are respectively connected to the driving electrode patterns and respectively extend from the first configuration region to the second configuration region. The shielding layer shields the conductive lines and exposes the driving electrode patterns. The electrophoretic display substrate includes a second base material located opposite to the first base material, an electrode layer, and display media. The electrode layer is disposed on the second base material and between the first and second base materials.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Abstract: A multimedia file sharing method and a system thereof are provided herein, which applies the virtual file technology to achieve near real time multimedia sharing and transparent receiving functions. In the method, an interface software system is established through a network to speed up playing of multimedia files by different multimedia players. The interface software provides a speeding up and near real time multimedia playing effect for sharing multimedia through the network, by which for different transmissions of multimedia files or for playing multimedia files with different formats, the multimedia player is not necessary to modify or add the software of the players to meet the streaming protocols or container. In addition, the interface software is capable of providing the effect of playing the multimedia files by the players with satisfied quality and near real time performance.

Abstract: A module for data center is presented, which is used for heat sinking of a heat source. The module for data center includes a first chamber, a second chamber, and a heat pipe. The heat source is positioned in the first chamber. The second chamber is adjacent to the first chamber. In addition, the heat pipe has an evaporation end positioned inside the first chamber and a condensation end positioned inside the second chamber. The heat pipe absorbs the heat energy in the first chamber with the evaporation end, transfers the heat energy to the condensation end, and eliminates the heat energy with the condensation end.

Abstract: A display device includes a driving layer and a displaying layer disposed on the driving layer. The driving layer includes a lower substrate, a number of driving segments and a number of conducting wires. The lower substrate has a first surface. The driving segments and the conducting wires both are disposed on the first surface of the lower substrate. The driving segments are connected to the conducting wires in a one-to-one manner. A line width of each of the conducting wires is less than 50 microns. The display device has a high resolution. A method for manufacturing the display device is also provided.

Abstract: A display device includes a driving layer and a displaying layer disposed on the driving layer. The driving layer includes a lower substrate, a number of driving segments and a number of conducting wires. The lower substrate has a first surface. The driving segments and the conducting wires both are disposed on the first surface of the lower substrate. The driving segments are connected to the conducting wires in a one-to-one manner. A line width of each of the conducting wires is less than 50 microns. The display device has a high resolution. A method for manufacturing the display device is also provided.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.