Abstract: Embodiments of the present disclosure disclose a memory system and operation method thereof, a memory controller and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, and m is a positive integer greater than 1. The operation method includes: determining, by the peripheral circuit, (n+1)th group of page data according to a received prefix command and received n groups of page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of page data and the (n+1)th group of page data into the memory cell array to generate 2n different data states in the memory cell array.

Abstract: A wellbore is plugged using a bismuth alloy. In one embodiment, the bismuth alloy comprises an alloy of bismuth and tin. In another embodiment, the bismuth alloy comprises an alloy of bismuth and silver. The wellbore can be arranged so that a liquid bismuth alloy sets with an excess pressure of the plug relative to the borehole fluid pressure along a desired seal height distance. Other aspects are described and claimed.

Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.

Abstract: The present disclosure provides a vehicle positioning device for vehicle vision calibration, a positioning adjustment method, and a positioning adjustment system. The vehicle positioning device includes a base, a chassis, a translation mechanism and a rotation mechanism. A to-be-calibrated vehicle is placed onto the chassis, and the chassis is provided with a stopper. The translation mechanism is arranged between the chassis and the base, and configured to drive the chassis to move in an X-axis direction in a three-dimensional coordinate system relative to the base in accordance with a translation control instruction. The rotation mechanism is arranged between the chassis and the base, and configured to drive the chassis to rotate about a Z-axis in the three-dimensional coordinate system relative to the base in accordance with a rotation control instruction.

Abstract: A rock direct tensile test platform suitable for all material test machines includes a support frame. A top of the support frame is fixed with a top plate, and a bearing plate is provided above the top plate. The bearing plate is provided with a plurality of vertical force transferring rods. The force transferring rods vertically penetrate through the top plate and have a sliding fit with the top plate. Lower ends of the force transferring rods are provided with a tensile base. A top of the tensile base is provided with a lower clamp holder. A bottom of the top plate is provided with an upper clamp holder, and a clamp center of the upper clamp holder coincides with a clamp center of the lower clamp holder.

Abstract: A direct tensile and acoustic testing machine under rock seepage includes a sample and a support frame. A top of the support frame is fixed with a top plate, a bearing plate is provided above the top plate, the bearing plate is provided with a plurality of vertical force transferring rods, the force transferring rods vertically penetrate through the top plate and sliding fit with the top plate, lower ends of the force transferring rods are provided with a tensile base, a top of the tensile base is provided with a lower clamp holder, a bottom of the top plate is provided with an upper clamp holder, and a clamp center of the upper clamp holder overlaps with a clamp center of the lower clamp holder. An acoustic component and a seepage component are provided in the upper clamp holder and the lower clamp holder.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: An electronic device is provided, including: a plurality of antennas, a switch, a sensor, a wireless communication transceiver, and a processor, electrically connected to antennas, the switch, the sensor, and the wireless communication transceiver, and configured to execute an antenna selection procedure according to a scenario of the electronic device, to connect at least one of the antennas to the sensor or the wireless communication transceiver through the switch.

Abstract: A circuit board includes a substrate, a driver circuit, at least one light-emitting element, a grounding circuit, and an antenna unit. The substrate includes a first circuit layer and a second circuit layer. The driver circuit is located on the first circuit layer. The light-emitting element is located on the first circuit layer and is electrically connected to the driver circuit, so that the driver circuit controls the light-emitting element to emit light. The grounding circuit is located on the second circuit layer and is electrically connected to the driver circuit. The grounding circuit includes a plurality of conductive traces, and the conductive traces are arranged toward one side to form a clearance area on the second circuit layer. The antenna unit is located on the first circuit layer and corresponds to the clearance area to receive and transmit a radio frequency signal.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Abstract: Related are a CSPG4-targeting humanized chimeric antigen receptor and applications thereof, comprising a humanized anti-CSPG4 binding domain, a hinge region, a transmembrane domain, and a signal transduction domain. The anti-CSPG4 binding domain comprises an anti-CSPG4 antibody or antigen binding part. Related are an immune effector cell expressing the CSPG4-targeting humanized chimeric antigen receptor and applications of the cell.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.

Abstract: In a method of manufacturing a semiconductor device, an initial pattern layout is obtained. The initial pattern layout incudes fin patterns which include active fin patterns to be formed as active fin structures and dummy fin patterns not to be formed as actual fin structures or to be removed. The locations of the fin patterns are modified, as follows. A space between adjacent active fin patterns is increased by a first amount, a space between the dummy fin patterns is decreased by a second amount, and a space between one of the dummy fin patterns and one of the active fin patterns adjacent to the one of the dummy fin patterns is decreased by a third amount. Mandrel patterns are placed so that the fin patterns of which locations are modified are placed along longitudinal edges of the mandrel patterns.

Abstract: An approach for the task-oriented user guidance is provided. The approach comprises receiving a query from a user to accomplish a task utilizing an application. The approach comprises determining one or more related pages of the application, wherein one or more keywords of the one or more related pages of the application match with one or more keywords of the query. The approach further comprises determining possible paths passing the one or more related pages of the application based on page relationship of the application. The approach further comprises determining one or more paths from the possible paths according to weights of the paths. The approach further comprises presenting the one or more paths to the user. The keywords of the page, the page relationship and the weights of the paths are determined based on page information of the application.

Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.

Abstract: A three-dimensional electronic component includes a first surface, a second surface, a third surface, and a fourth surface, and an antenna structure. The antenna structure includes a first radiating metal portion, a second radiating metal portion, an adjusting metal branch, a first ground connection portion, a second ground connection portion, a feed point, and a ground point. The first radiating metal portion on the first surface extends to the second surface. The second radiating metal portion on the first surface extends to the third surface. A gap is between the first radiating metal portion and the second radiating metal portion. The adjusting metal branch on the first surface is connected to the first radiating metal portion. The feed point on the first radiating metal portion is close to the gap. The ground point on the second radiating metal portion is close to the gap.