Abstract: A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.

Abstract: An insulated glove, including a covering, a lining and a plurality of heat insulators. The lining is sheathed in the covering, and the lining and the covering form a sandwich structure. Each of the heat insulators includes a first connecting end and a second connecting end which are respectively connected to the covering and the lining, so that the heat insulators are located in the sandwich structure. A cavity capable of insulating heat is formed between the heat insulators, the lining and the covering. The glove has a simple and reasonable structure and is flexible and convenient to use, which has good heat insulation and anti-scald effect, as well as an anti-shock effect.

Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Abstract: The present disclosure provides a MIMO antenna device and a mobile communication device which comprises a metal shell and a metal piece, the metal shell comprises a metal back plate and a metal frame which are integrally formed, the metal frame surrounds the metal back plate, the metal piece and the metal shell enclose to form a metal cavity, the metal cavity comprises a battery region used to place a battery assembly and a non-battery region outside the battery region; a metal isolate wall is provided between the metal shell and the metal piece, the metal isolate wall partitions the metal cavity into a first cavity and a second cavity, the first cavity contains the battery region; a first feed unit feeds toward the first cavity to form a first antenna; and a second feed unit feeds toward the second cavity to form a second antenna.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.

Abstract: The present invention is related to a galactolipids-enriched plant extract, prepared by extracting a plant sample selected from a group consisting of: Gynura divaricata subsp. formosana (Asteraceae) (GD), Murdannia bracteata (C. B. Clarke) J. K. Morton ex D. Y. Hong (Commelinaceae) (MB), and Crassocephalum rabens S. Moore (Asteraceae) (CR) with a series of solvents. A pharmaceutical, nutritional, or healthcare composition for protecting or treating acute fulminant hepatitis, for protecting or treating sepsis or related indication thereof, and a composition for skin whitening are also provided herein. These compositions all comprise effective amounts of the galactolipids-enriched plant extracts or purified compounds thereof as bioactive ingredients.

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Abstract: An intelligently distributed stage data mining system is disclosed herein, including an intelligent central server, a first WLAN receiving and transmitting unit, a local cluster control unit, a second WLAN receiving and transmitting unit, a third WLAN receiving and transmitting unit, a self-adaptive multi-dimensional transmission processing unit, a plurality of ZigBee receiving and transmitting units and a distributed data extraction unit. The intelligent central server is used for sending data acquisition and stage correction instruction to the local cluster control unit, and for receiving the stage real-time data uploaded by the self-adaptive multi-dimensional transmission processing unit. The local cluster control unit is used for receiving the data acquisition instruction sent by the intelligent central server, and forwarding instructions to the self-adaptive multi-dimensional transmission processing unit.

Abstract: A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Abstract: A new class of sesquiterpene derivative useful for treating cancerous and inflammatory diseases are disclosed. These deoxyelephantopin derivatives are effective in suppressing proliferation, migration, mobility, invasion, growth, and/or metastasis of cancer cells in a patient, or useful for enhancing an anti-proliferative effect of another anti-cancer drug on cancer cells when treating a patient, or for sensitizing and/or enhancing an anti-cancer effect of a gluthathione synthesis blocker on inhibition of triple negative breast cancer cell activity, or for treatment and/or prophylaxis of lipopolysaccharide-stimulated inflammatory response in a patient, or for all of the above. Also disclosed are methods of preparing the deoxyelephantopin derivatives.

Abstract: The present invention is related to a galactolipids-enriched plant extract, prepared by extracting a plant sample selected from a group consisting of :Gynura divaricata subsp. formosana (Asteraceae) (GD), Murdannia bracteata (C. B. Clarke) J. K. Morton ex D. Y. Hong (Commelinaceae) (MB), and Crassocephalum rabens S. Moore (Asteraceae) (CR) with a series of solvents. A pharmaceutical, nutritional, or healthcare composition for protecting or treating acute fulminant hepatitis, for protecting or treating sepsis or related indication thereof, and a composition for skin whitening are also provided herein. These compositions all comprise effective amounts of the galactolipids-enriched plant extracts or purified compounds thereof as bioactive ingredients.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.