Abstract: An intelligent wearable outfit, and an external information platform and a computer program product which are in conjunction with the intelligent wearable outfit, provide various functional modules for measuring physiological signals in a modular design. An appropriate functional module (or even more than one functional module if desired) may be selected therefrom and arranged in the wearable outfit to extend and change functions of the wearable outfit, making the intelligent wearable outfit suitable for most users who can manage personal health appropriately.

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract: An aspect includes a computer system with a widget hierarchical layout correlation parser to: receive widget objects and widget object methods; and generate, based on the widget objects and widget object methods and using a symbol table derived from semantic analysis, a multi-level tree-like widget layout structure including nodes respectively corresponding to the widget objects and relationships between the nodes, with: (i) the relationships between the nodes including relationship types including: siblings, parents, children and self, and (ii) a determination of relationships for each node determines any parent(s), sibling(s) and/or children within one level of the multi-level tree-like widget layout structure. For each given widget object, a resource string reference parser parses source code of the given widget object to: collect setMethods arguments for the given widget object, and trace back to a message key in a resource file associated with the given widget object according to the symbol table.

Abstract: Embodiments of translation verification testing are provided. An aspect includes reading a symbol table and a syntax tree to which source code corresponds. Widget objects and widget object methods are obtained in the symbol table. The widget objects and widget object methods are organized into a widget structure tree according to a code calling order in the syntax tree. An index file corresponding to the source code is generated by using the symbol table, the widget structure tree and resource files, where the index file records relationships between the widget objects.

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract: Aspects include controlling asynchronous call return in a program. At least one asynchronous call is detected in the program. Execution of the program is stopped at a breakpoint in response to detecting that the breakpoint is set in the program. At least one callback corresponding to the at least one asynchronous call is obtained. The at least one callback is inserted into one or more specified positions of the program respectively according to a user selection. Execution of the program continues from the breakpoint in response to the insertion of the at least one callback into the program.

Abstract: In a method 1100 of linking model instances to packages, a service instantiation request is received 1110. The service instantiation request is associated 1120 with service model instance. Linked instances are generated 1130 between the service model instance and available packages. The linked instances are evaluated 1140. Based on the evaluating, a most efficient linked instance of the linked instances is selected 1150 to include in a bound package model of the service instantiation request.

Abstract: A superjunction device in which corner portions of each annular-shaped second trench are composed of a plurality of alternately arranged first sides and second sides. The first sides are parallel to a plurality of parallel arranged first trenches in a current-flowing area, while the second sides are perpendicular to the first sides and the first trenches. Such design ensures that Miller indices of sidewalls and bottom face of any portion of each second trench belong to the same family of crystal planes. Moreover, with this design, the corner portions of the second trenches can be filled with a silicon epitaxial material at the same rate with the rest portions thereof, which ensures for the second trenches to be uniformly and completely filled without any defects in the corner portions and hence improve the performance of the superjunction device.

Abstract: Embodiments of translation verification testing are provided. An aspect includes reading a symbol table and a syntax tree to which source code corresponds. Widget objects and widget object methods are obtained in the symbol table. The widget objects and widget object methods are organized into a widget structure tree according to a code calling order in the syntax tree. An index file corresponding to the source code is generated by using the symbol table, the widget structure tree and resource files, where the index file records relationships between the widget objects.

Abstract: Aspects include controlling asynchronous call return in a program. At least one asynchronous call is detected in the program. Execution of the program is stopped at a breakpoint in response to detecting that the breakpoint is set in the program. At least one callback corresponding to the at least one asynchronous call is obtained. The at least one callback is inserted into one or more specified positions of the program respectively according to a user selection. Execution of the program continues from the breakpoint in response to the insertion of the at least one callback into the program.

Abstract: A method of preventing dopant from diffusing into atmosphere in a BiCMOS process is disclosed. The BiCMOS process includes the steps of: depositing a first silicon oxide layer and a silicon nitride layer over surface of a silicon substrate; etching the silicon substrate to form a plurality of shallow trenches therein; depositing a second silicon oxide layer over surface of the silicon substrate and forming silicon oxide sidewalls over inner side faces of each of the plurality of shallow trenches; forming a heavily doped pseudo buried layer under a bottom of one of the plurality of shallow trenches by implanting a dopant with a high concentration; performing an annealing process to promote diffusion of the dopant contained in the pseudo buried layer, wherein the method includes growing, by thermal oxidation, a silicon oxide layer over a bottom of each of the plurality of shallow trenches during the annealing process.

Abstract: A synthesis method of Sigma-Delta modulator capable of relaxing circuit specification and reducing power consumption, comprising the following steps: firstly, set a target bandwidth and a target performance; upon obtaining a Noise Transfer Function (NTF), perform coefficient synthesis a first time, to ascertain a plurality sets of first performance results corresponding to said NTF, and obtain a plurality sets of first circuit specifications fulfilling said target performance, through analyzing circuit non-ideal effect of said first performance results. Next, increase an oversampling ratio of parameters, to obtain a plurality sets of second performance results, and a plurality sets of second circuit specifications. Then, increase quantizer bit number, and increase attenuation quantity, to obtain a plurality sets of third circuit specifications. Finally, compare said first, second and third circuit specifications, to select one of greatest variation to perform calibrations.

Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.

Abstract: A method for synthesizing Sigma-Delta Modulator, which selects at least a system configuration and parameters, substitute a noise transfer formula into said system configuration to obtain coefficients. Using a least-square method to obtain a stability equation, and calculating an ideal performance of said system configuration based on said parameters and stability equation. Substitute the coefficients into non-ideal effect models, and acquire the circuit specification of an operation amplifier in said system configuration in a hierarchic approach to calculate the circuit performance of the operation amplifier. Determine whether said circuit specification of said operation amplifier has a solution based on related specification equation. If an answer is positive, calibrate length and width of transistors in said operation amplifier, until it meets the requirements of said circuit specification.

Abstract: A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.

Abstract: A method of forming silicide layers is disclosed, the method including: providing a silicon substrate which includes at least one first region and at least one second region; depositing a dielectric layer over the silicon substrate; forming at least one opening having a great width/depth ratio in the dielectric layer above the at least one first region, and forming at least one opening having a small width/depth ratio in the dielectric layer above the at least one second region; depositing a metal and performing a high-temperature annealing to form a thick silicide layer in each of the at least one opening above each of the at least one first region and to form a thin silicide layer in each of the at least one opening above each of the at least one second region; removing the remaining metal not formed into the silicide layers.

Abstract: An ultra high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which, a collector region is formed between two isolation structures; a pseudo buried layer is formed under each isolation structure and each side of the collector region is connected with a corresponding pseudo buried layer; a SiGe field plate is formed on each of the isolation structures; each pseudo buried layer is picked up by a first contact hole electrode and each SiGe field plate is picked up by a second contact hole electrode; and each first contact hole electrode is connected to its adjacent second contact hole electrode and the two contact hole electrodes jointly serve as an emitter. A manufacturing method of the ultra high voltage SiGe HBT is also disclosed.