Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes a substrate, a dielectric layer over the substrate, memory cells disposed in the dielectric layer, and a metal line above the memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. A bottom surface of the metal line has a continuously flat portion that directly interfaces each of the top electrodes of the memory cells.

Abstract: The disclosure is a power tool. The adaptor head includes a seat, a connecting sleeve, an inserting hole and a rolling ball trench. The inserting hole is disposed in the connecting sleeve. The rolling ball trench communicates with the inserting hole. The rolling balls are movably accommodated in the rolling ball trench and include a lower rolling ball which may partially fall in the inserting hole and upper rolling balls. The upper rolling balls include a front rolling ball and a rear rolling ball. The sleeve includes a blocking block and a buffering trench and moves relative to the seat to make the front rolling ball blocked by the blocking block or fall in the buffering trench. The flexible ring flexibly presses the rear rolling ball.

Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.

Abstract: Disclosed is the new use of a JAK3/JAK1/TBK1 selective inhibitor. Animal experiments have proven that the JAK3/JAK1/TBK1 selective inhibitor has significant treatment and improvement effects on autoimmune skin diseases, especially Alopecia areata and inflammatory skin diseases, such as atopic dermatitis.

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Abstract: A package structure is provided. The package structure includes a cell chip structure having a memory cell and a multiplexer. The package structure includes an intermediate chip structure directly bonded to the cell chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding and having a sense amplifier and a driver element. The intermediate chip structure does not have a memory cell. The package structure includes a calculating chip structure bonded to the intermediate chip structure and having a calculating element.

Abstract: An apparatus including an integrated reference electrode and a fluid dispenser is described. The reference electrode includes a body and a tip. The fluid dispenser at least partially surrounds the tip of the reference electrode and includes an inlet, a chamber, and an outlet. The fluid dispenser is configured to receive a fluid sample from the inlet to the chamber and form a droplet of the fluid sample through the outlet so that the droplet is in fluidic contact with the tip of the reference electrode and associated with a known potential determined by the reference electrode.

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: An approach is described for a user equipment (UE) that includes radio front end circuitry and processor circuitry. The front end circuitry receives an indication from a network entity node, wherein the indication is indicative of a first fraction for a first radio resource management (RRM) procedure and a second fraction for a second RRM procedure. The processor circuitry performs a first measurement of the first RRM procedure in a first fraction of a measurement period. The processor circuitry further performs a second measurement of the second RRM procedure in a second evaluation period, wherein the second evaluation period is the second fraction of the measurement period.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

Abstract: An apparatus and system for a unified transmission configuration indicator (TCI) state switch requirement are described. Both radio resource management and TCI state switch delay requirements are described. The UL TCI state switch delay requirement may depend on whether a downlink (DL) reference signal (RS) associated with the UL TCI state satisfies known conditions, as well as whether a joint or separate TCI mode is being used. In the separate TCI mode. the delay requirement may include timing between a DL data transmission and acknowledgement, and also include a time for receive beam refinement in frequency range2. In the joint TCI mode. the UL and DL TCI state switch delay requirement—due may be the same or may be the same as the separate TCI mode.

Abstract: A circuit board structure including a first circuit board, a second circuit board, a conductive coil and a first molding compound and a manufacturing method thereof. The first circuit board has a first side surface. The second circuit board has a second side surface facing the first side surface and being spaced apart from the first side surface. The conductive coil is in a spiral shape and includes a first coil pattern and a second coil pattern. The first coil pattern is disposed in the first circuit board. The second coil pattern is disposed in the second circuit board. The first coil pattern is electrically connected to the second coil pattern. The first molding compound is magnetic and filled in a gap located between the first side surface and the second side surface. The conductive coil surrounds at least a part of the first molding compound.

Abstract: A manufacturing method of a tiling electronic device includes the following steps. A first electronic panel is provided. The first electronic panel includes multiple first bumps and multiple first conducting lines, and the first bumps and the first conducting lines are disposed on a side surface of the first electronic panel. A second electronic panel is provided. The second electronic panel includes multiple second bumps and multiple second conducting lines, and the second bumps and the second conducting lines are disposed on a side surface of the second electronic panel. The first electronic panel and the second electronic panel are coupled through the first bumps and the second bumps. Multiple conducting elements are formed, so that the first conducting lines are electrically connected with the second conducting lines through the conducting elements after the first electronic panel and the second electronic panel are coupled.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

Abstract: A power apparatus applied in a solid state transformer structure includes an AC-to-DC conversion unit, a first DC bus, and a plurality of bi-directional DC conversion units. First sides of the bi-directional DC conversion units are coupled to the first DC bus. Second sides of the bi-directional DC conversion units are configured to form at least one second DC bus, and the number of the at least one second DC bus is a bus number. The bi-directional DC conversion units receive a bus voltage of the first DC bus and convert the bus voltage into at least one DC voltage, or the bi-directional DC conversion units receive at least one external DC voltage and convert the at least one external DC voltage into the bus voltage.

Abstract: Embodiments of this application disclose a backscatter communication method and a related apparatus. The method includes: An excitation device determines a first sequence, generates a first signal, and sends the first signal, where the first signal carries the first sequence; after receiving the first signal, a backscatter device modulates backscatter device data onto the received first signal to obtain a second signal, and backscatters the second signal, to implement first scrambling on the backscatter device data by using the first sequence; and a receiving device determines the first sequence, receives the second signal from the backscatter device, and demodulates the received second signal based on the first sequence, to obtain the backscatter device data carried on the second signal.