Abstract: A manufacturing method of an optical device includes: providing a lower transparent substrate; wherein the lower transparent substrate includes an upper surface; providing a quantum dot film element and a glue-material enclosure wall disposed on the upper surface; wherein the glue-material enclosure wall surrounds the quantum dot film element; providing an upper transparent substrate covering the quantum dot film element and the glue-material enclosure wall, such that the quantum dot film element and the glue-material enclosure wall are sandwiched between the lower transparent substrate and the upper transparent substrate; and cutting the lower transparent substrate and the upper transparent substrate to form a lower protective film and an upper protective film corresponding to the quantum dot film element, so as to obtain the optical device including the lower protective film, the upper protective film, the quantum dot film element, and the glue-material enclosure wall.

Abstract: A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. A seal ring within the semiconductor device is extended to include a first bond metal within a bonding layer and bonded to a second bond metal over the semiconductor substrate. Such a seal ring provided a more complete protection from cracking and delamination.

Abstract: A method, a network device, and a non-transitory computer-readable storage medium are described in relation to a low latency, low loss, and scalable throughput (LI4S)-triggered prioritized connection service. The LI4S-triggered prioritized connection service may enable an evolved packet data gateway (ePDG) to provision prioritized and non-prioritized tunnels with end devices via untrusted wireless local area networks. The prioritized tunnel may support LI4S or another quality of service in which the ePDG may provide prioritized data forwarding. The end device may transmit a request that includes priority data.

Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

Abstract: A method, applied to an electronic device comprising a camera and a temperature sensor, wherein the method comprises displaying a temperature measurement interface, receiving, from a user, a temperature measurement operation, measuring, in response to the temperature measurement operation and using the temperature sensor, a first temperature of a measured object, collecting, using the camera, a picture of the measured object, determining, based on the picture, a type of the measured object, matching, based on the type, a first temperature algorithm for the measured object, and determining, based on the first temperature and first algorithm, a second temperature of the measured object.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: Disclosed are a method and an apparatus for detecting a wearing state of an earphone, an earphone, and a storage medium. The method includes: obtaining a request for detecting the wearing state of the earphone; performing audio collection by a feedback microphone of the earphone to obtain a feedback audio signal; determining a frequency of the audio, and determining a target frequency with a power meeting a preset condition in the feedback audio signal based on the frequency and an audio collection parameter of the feedback microphone; performing a power spectrum analysis on the feedback audio signal to obtain a power spectrum of the feedback audio signal; determining target power information of the target frequency from the power spectrum; and in response to the target power information being not less than a maximum power threshold value set for the target frequency, determining that the wearing state is in-ear state.

Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.

Abstract: A heat pipe comprises a flat tube and a wick structure. The flat tube includes a hollow chamber and has a front and a rear sealed ends along an axial direction. The wick structure is disposed in the hollow chamber and extended along the axial direction of the flat tube. The wick structure is divided into a front, a middle and a rear sections sequentially along the axial direction. The front section is near the front sealed end, the rear section is near the rear sealed end. The front, middle and rear sections have a maximum length parallel to the width direction, respectively. The maximum length of the front section is greater than that of the middle section, and the maximum length of the middle section is greater than that of the rear section.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: A camera module includes a circuit board, a lens assembly, and a first board. The circuit board includes a first surface, a second surface opposite to the first surface, a first sidewall, and a second sidewall opposite to the first sidewall. Each of the first sidewall and the second sidewall connects the first surface to the second surface. The lens assembly is disposed on the first surface. The first board is connected to the first sidewall. The first board is inclined or perpendicular to the first surface. The first board is disposed on a side of the lens assembly.

Abstract: An electronic device includes at least a housing, a mainboard, a conductive coil, and a conductive adapter. The housing includes an inner surface and an outer surface provided opposite to each other. The mainboard is arranged on the inner surface. The conductive coil is arranged on the inner surface and is integrally arranged with the housing. The conductive coil includes a winding portion, an outer connection terminal, and an inner connection terminal. In a radial direction of the winding portion, the mainboard is located at an outer side of the winding portion. The outer connection terminal is connected to the winding portion and is located at the outer side of the winding portion. The outer connection terminal is electrically connected to the mainboard.

Abstract: The present disclosure provides a correction system and method for correcting a semiconductor circuit. The correction system includes a plurality of redundant circuit units, a plurality of switching circuit units and a control circuit. The redundant circuit units are coupled to the semiconductor circuit. The switching circuit units are coupled to the redundant circuit units and a plurality of basic circuit units of the semiconductor circuit. The control circuit is coupled to the semiconductor circuit and the switching circuit units, is configured to obtain a noise signal of the semiconductor circuit, is configured to determine whether the semiconductor circuit passes a noise test by recognizing a characteristic of the noise signal, and is configured to replace one of the basic circuit units with one of the redundant circuit units by controlling the switching circuit units when the semiconductor circuit does not pass the noise test.

Abstract: This disclosure is directed to a solid state transformer and a printed circuit board stack-up structure, the printed circuit board stack-up structure has a plate, a power device, a thermally conductive insulating layer, a heat diffusion layer and a thermal conductor. The plate has a first surface and a second surface respectively disposed at two sides. The power device is arranged on the first surface. The thermally conductive insulating layer is pressed to combine with the second surface and cover the second surface. The heat diffusion layer is pressed to combine with the thermally conductive insulating layer and cover the thermally conductive insulating layer. The thermal conductor is embedded in the plate and respectively connected to the power device and the thermally conductive insulating layer.

Abstract: A circuit board structure includes a core, a wiring layer and a buried passive component. The wiring layer and the buried passive component are disposed on the core, and the buried passive component is electrically connected to the wiring layer. The buried passive component includes a first spiral metal layer, a second spiral metal layer and a dielectric interlayer. The first spiral metal layer is intertwined with the second spiral metal layer. The dielectric interlayer is disposed between the first spiral metal layer and the second spiral metal layer. The first spiral metal layer and the second spiral metal layer are spaced apart by the dielectric interlayer at least in the core.