Patents by Inventor Hua Huang

Hua Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250144755
    Abstract: A screw tightening device includes a fixing mechanism extend in a first direction and including first and second ends arranged opposite to each other in the first direction, a regulating mechanism arranged at the first end and including a regulating port, a screw feeding mechanism arranged at the regulating mechanism and configured to convey a screw to the regulating port, a tightening mechanism arranged at the fixing mechanism and configured to drive the screw to rotate, a first driving mechanism arranged at the second end and configured to be drivingly connected to the tightening mechanism and to drive the tightening mechanism to move in the first direction to the regulating port, and a second driving mechanism arranged at the second end and configured to be drivingly connected to the tightening mechanism and to drive the tightening mechanism to move in the first direction to extend out of the regulating port.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Zhiqiang SUN, Xueqing GONG, Hua HUANG, Yang LI, Fanke CHEN
  • Publication number: 20250150554
    Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to teleconferencing and, more specifically, to the gathering and conveying of information over a teleconference by a digital delegate. A computer-implemented system can comprise a memory that can store computer executable components. The computer-implemented system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a digital delegate component that accesses a teleconference via a computer application as a teleconference participant and an analysis component that analyzes teleconference monitoring information of the teleconference to determine responses to one or more defined points of interest determined by a meeting invitee.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 8, 2025
    Inventors: Allen Vi Cuong Chan, Yazan Obeidi, Sebastian Carbajales, Benjamin Luong, Will Wu, Paul Ferski, Hua Huang, Lionel Wu
  • Publication number: 20250151475
    Abstract: A light-emitting chip includes a light-emitting unit, first and second electrode units. The light-emitting unit includes first and second conductivity type semiconductor layers and an active layer. The first electrode unit includes two first electrodes which are spaced apart from each other by a first distance, and which are electrically connected to the first conductivity type semiconductor layer. The second electrode unit includes two second electrodes electrically connected to the second conductivity type semiconductor layer. The first and second electrode units are spaced apart from each other by a second distance, and the first distance is greater than the second distance.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: Xiaoqiang ZENG, Kunte LIN, Jianfeng YANG, Kaiqing XU, Shao-Hua HUANG
  • Patent number: 12289979
    Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
  • Publication number: 20250121416
    Abstract: Disclosed is a cleaning method and system. The cleaning system comprises a control device, a quick swap platform, and a clamping jaw device. The control device of the cleaning system determines whether there is a target tool on the quick swap platform according to target first-article information when receiving the target first-article information, wherein the target first-article information represents blueprint information of a first-article battery module; and the target tool is a tool configured to be cleaned instead of the first-article battery module. The control device controls, when it is determined that there is the target tool on the quick swap platform, the clamping jaw device to grab the target tool for cleaning, which can effectively improve operation convenience without affecting normal production and improve production efficiency.
    Type: Application
    Filed: August 27, 2024
    Publication date: April 17, 2025
    Inventors: Hua Huang, Yuming Xie, Xueqing Gong, Fanke Chen, Haoyuan Chen
  • Publication number: 20250125313
    Abstract: An electronic package is provided and includes a first circuit structure having opposite first and second surfaces; an electronic component set including a first electronic component and a second electronic component and having opposite first and second sides, wherein the first electronic component is located on the first side and has opposite first active surface and first inactive surface, the second electronic component has opposite second active surface and second inactive surface, and a part of the second active surface protrudes and is exposed from an outside of the first electronic component to electrically connect to the first surface; and an encapsulating layer defining opposite first encapsulating surface and second encapsulating surface, wherein the second encapsulating surface is connected to the first surface. As such, the overall height of the electronic package can be reduced and the heat dissipation efficiency of the electronic package can be improved also.
    Type: Application
    Filed: August 16, 2024
    Publication date: April 17, 2025
    Inventors: I-Tang LIU, Hsiang-Hua HUANG, Yu-Min LO
  • Publication number: 20250123719
    Abstract: An infrared touch screen and a display device. The infrared touch screen comprises: a cover plate having a light incident surface and a light emergent surface that are connected by a first side face; an infrared light source disposed on a side of the light incident surface of the cover plate; a first frame; and a first infrared filter strip that is connected to the first frame and is disposed on a side of a first side surface of the cover plate, the first infrared filter strip being used for converting at least part of infrared light emitted by the infrared light source to propagate in a direction parallel to the light emergent surface on a side of the light emergent surface of the cover plate.
    Type: Application
    Filed: August 8, 2022
    Publication date: April 17, 2025
    Applicants: SHENZHEN HUASHENG SOFTWARE TECHNOLOGY CO., LTD., TCL BUSINESS INFORMATION TECHNOLOGY (HUIZHOU) CO., LTD.
    Inventors: Xiongbo YE, Yiming LIU, Hua HUANG
  • Publication number: 20250123450
    Abstract: Some embodiments relate to an integrated circuit (IC) device that includes a first substrate including an optical lens at a frontside surface of the first substrate, an electrical IC structure disposed proximate a backside surface of the first substrate, and a photonic IC structure disposed proximate a backside surface of the electrical IC structure. The photonic IC structure includes a second substrate providing a backside surface of the photonic IC structure; a photodetector, a grating coupler, and an inverse grating coupler disposed over a frontside surface of the second substrate; and a reflector disposed at a frontside surface of the photonic IC structure. The grating coupler and the inverse grating coupler are configured to direct light from the optical lens and the backside surface of the second substrate, respectively, to the photodetector. The reflector is configured to direct light from the inverse grating coupler back to the inverse grating coupler.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 17, 2025
    Inventors: Xin-Hua Huang, Kuo-Hao Lee, Jung-Kuo Tu, Kejun Xia, Tse-En Chang
  • Publication number: 20250125398
    Abstract: Embodiments of the present disclosure provide a quick-change platform, a battery production line and a control method. The quick-change platform includes a tray set. In a first pick-and-place state, the tray set is located in a first pick-and-place position, so as to enable the tray set to receive the target objects removed from a battery module clamp, or enable a battery module transport apparatus to pick the target objects placed on the tray set. In a second pick-and-place state, the tray set is located in a second pick-and-place position, so as to remove the target objects on the tray set, or place the target objects on the tray set.
    Type: Application
    Filed: September 18, 2024
    Publication date: April 17, 2025
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Kai WU, Hua HUANG, Yanlin SUN, Yuming XIE, Wanjin GUO
  • Publication number: 20250121505
    Abstract: A pick and place device comprises at least one pair of pick and place assemblies and at least two detectors. Each pick and place assembly comprises: a first guide rail extending in a first direction, a second guide rail extending in a second direction intersecting the first direction, a clamping assembly comprising first and second clamping members, and a connecting member connected to the first guide rail and the second guide rail. The first and second clamping members are arranged on the first and second guide rails, respectively, and are movable closer to or away from each other. The connecting member is configured to be movable along the first guide rail and the second guide rail. Each detector is arranged on the respective connecting member and is configured to detect whether there is an obstacle within a specified range in a preset direction.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 17, 2025
    Inventors: Hua HUANG, Yuming XIE, Xueqing GONG, Fanke CHEN, Wanjin GUO
  • Publication number: 20250118587
    Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 10, 2025
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Chang-Chen Tsao
  • Publication number: 20250105174
    Abstract: A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. A seal ring within the semiconductor device is extended to include a first bond metal within a bonding layer and bonded to a second bond metal over the semiconductor substrate. Such a seal ring provided a more complete protection from cracking and delamination.
    Type: Application
    Filed: January 18, 2024
    Publication date: March 27, 2025
    Inventors: Chen Hua Huang, Cheng-Hsien Hsieh, Li-Han Hsu
  • Patent number: 12262642
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • Patent number: 12255387
    Abstract: An electronic device includes at least a housing, a mainboard, a conductive coil, and a conductive adapter. The housing includes an inner surface and an outer surface provided opposite to each other. The mainboard is arranged on the inner surface. The conductive coil is arranged on the inner surface and is integrally arranged with the housing. The conductive coil includes a winding portion, an outer connection terminal, and an inner connection terminal. In a radial direction of the winding portion, the mainboard is located at an outer side of the winding portion. The outer connection terminal is connected to the winding portion and is located at the outer side of the winding portion. The outer connection terminal is electrically connected to the mainboard.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: March 18, 2025
    Assignee: Honor Device Co., Ltd.
    Inventors: Xuyang Wang, Hua Huang
  • Patent number: 12255062
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 12248247
    Abstract: Wire grid polarizer and manufacturing method thereof are provided, the wire grid polarizer includes: substrate; first wire grid formed on substrate, including first wire grid reflection strips arranged parallel to each other and at equal intervals; second wire grid formed at a side of first wire grid away from substrate, including second wire grid reflection strips arranged in parallel to each other and at equal intervals; second wire grid reflection strips are in one-to-one correspondence with first wire grid reflection strips; orthographic projections of second wire grid reflection strip onto substrate falls within orthographic projections of corresponding first wire grid reflection strip onto substrate; wire width of second wire grid reflection strip is less than that of first wire grid reflection strip; and wire spacing of second wire grid reflection strip is greater than that of the first wire grid reflection strip.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 11, 2025
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiao Zhang, Yongxing Liu, Jiahui Han, Hua Huang, Kang Guo, Xin Gu
  • Publication number: 20250077180
    Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ming-Hung Lin, Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, You-Yu Nian, Pei-Kuei Tsung, Jen-Wei Liang, Shu-Hsin Chang, En-Jui Chang, Chih-Wei Chen, Po-Hua Huang, Chung-Lun Huang
  • Publication number: 20250077282
    Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ming-Hung Lin, Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, You-Yu Nian, Pei-Kuei Tsung, Jen-Wei Liang, Shu-Hsin Chang, En-Jui Chang, Chih-Wei Chen, Po-Hua Huang, Chung-Lun Huang
  • Patent number: 12245515
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Patent number: D1067618
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 25, 2025
    Assignee: Zhejiang Zhengte Co., Ltd.
    Inventors: Hua Huang, Jian Lou