Abstract: A semiconductor device includes an isolation structure in a substrate. The semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. The semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. The semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.

Abstract: A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.

Abstract: This application provides a service widget display method, an electronic device, and a storage medium. The method includes: receiving a first operation of a user in a first state; displaying a first service widget in response to the first operation, where the first service widget includes a first target service; receiving a second operation of the user in a second state; and displaying a second service widget in response to the second operation, where the second service widget includes a second target service; and the first target service is different from the second target service, and one or more of the following information of the electronic device in the first state and the second state are different: a current location and current time of the electronic device.

Abstract: A fabricated rapid construction platform for a bridge, wherein the construction platform comprises a fixing frame, an upper-layer tubular pile position control structure (6), a lower-layer tubular pile position control structure (7), and a console; the fixing frame comprises a bottom rail platform (1), supporting posts (3), a top operation platform (2), and several supporting legs (4); the upper-layer tubular pile position control structure (6) and the lower-layer tubular pile position control structure (7) are provided between the bottom rail platform (1) and the top operation platform (2); the upper-layer tubular pile position control structure (6) comprises two sub-structures arranged symmetrically about the central axis of a second through hole, and each sub-structure comprises a braking device (61), a vertical control arm (63), and a horizontal control arm (62).

Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Abstract: An optical part includes a quantum dot film layer, a lower transparent film layer, and an outer protective film. The quantum dot film layer includes an upper surface, a lower surface, and a lateral surface. The lateral surface connects the upper surface with the lower surface, and the quantum dot film layer is a film containing light emitting semiconductor nanoparticles. The lower transparent film layer is disposed on the lower surface of the quantum dot film layer. The outer protective film directly or indirectly covers the upper surface of the quantum dot film layer, and extends to cover the lateral surface of the quantum dot film layer.

Abstract: A power apparatus applied in a solid state transformer structure includes an AC-to-DC conversion unit, a first DC bus, and a plurality of bi-directional DC conversion units. First sides of the bi-directional DC conversion units are coupled to the first DC bus. Second sides of the bi-directional DC conversion units are configured to form at least one second DC bus, and the number of the at least one second DC bus is a bus number. The bi-directional DC conversion units receive a bus voltage of the first DC bus and convert the bus voltage into at least one DC voltage, or the bi-directional DC conversion units receive at least one external DC voltage and convert the at least one external DC voltage into the bus voltage.

Abstract: A light-emitting diode includes: a substrate, an epitaxial layer and a protective layer; the epitaxial layer is disposed on the substrate and includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially in that order; the protective layer covers the epitaxial layer; the epitaxial layer is divided into chiplets, each chiplet includes transverse and longitudinal sidewalls intersecting in transverse and longitudinal directions, dicing channels are defined between adjacent chiplets, the dicing channels include transverse and longitudinal dicing channels extending respectively in the transverse and longitudinal directions, the protective layer covers the dicing channels and chiplet sidewalls, a patterned structure is disposed on the protective layer in an intersecting area of the transverse and the longitudinal dicing channels, and includes a groove extending toward the substrate.

Abstract: Disclosed are a light-emitting device with quantum dots and a manufacturing method thereof. The light-emitting device includes a light-emitting diode chip, a transparent barrier layer, a quantum dot film, and a transparent protective layer. The transparent barrier layer is disposed on the light-emitting diode chip. The quantum dot film is disposed on the transparent barrier layer, such that the light-emitting diode chip is separated from the quantum dot film by the transparent barrier layer. The transparent protective layer is disposed on the quantum dot film, such that the quantum dot film is encapsulated between the transparent barrier layer and the transparent protective layer.

Abstract: This application provides a wireless charging coil, and an electronic device and an antenna that include the wireless charging coil. The wireless charging coil includes a plurality of coil groups that are at a plurality of layers and that are connected in series, and an insulation layer that is disposed between two layers of the plurality of coil groups. The wireless charging coil includes a first area and a second area that is disposed at an outer periphery of the first area. A plurality of coil groups disposed in the second area are arranged at the plurality of layers, and each coil group includes a plurality of coils wound in parallel at one layer.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: An imaging lens system includes a lens barrel element and an imaging lens assembly disposed on the lens barrel element and including a first imaging lens element, a spacer element and a second imaging lens element. The spacer element has a second object-side contact surface corresponding to a first image-side contact surface of the first imaging lens element. The second imaging lens element has a third object-side contact surface corresponding to a second image-side contact surface of the spacer element. The lens barrel element and the spacer element form a buffer structure closer to an optical axis than the first image-side contact surface and including a first gap and a second gap located closer to the optical axis than the first gap. The first gap overlaps the third object-side contact surface in a direction parallel to the optical axis. A step difference is between the first and second gaps.

Abstract: A circuit board assembly with a fully embedded photosensitive chip which does not require an increase in board width for the re-routing of wires around the photosensitive chip includes a circuit board and a reinforced plate at a lower elevation which is connected to the circuit board. The circuit board defines a through hole and a plurality of conductive lines. The conductive lines or the portion of them which are cut off by the location of the through hole accommodating the chip are repeated by connecting lines carried on the reinforced plate, the plurality of connecting lines connects to and continues the conductive lines which are cut off by the hole.

Abstract: Provided are a display substrate, a method for manufacturing a display substrate and a display apparatus. The display substrate includes a base, a drive structure layer disposed on the base, a light emitting element disposed on the drive structure layer, an encapsulation layer disposed on the light emitting element, a circular polarizer layer disposed on the encapsulation layer, and a lens definition layer and a lens structure layer disposed on the circular polarizer layer. The light emitting element includes a pixel definition layer provided with a plurality of sub-pixel openings; the lens structure layer includes a plurality of lenses disposed at intervals, the lens definition layer is disposed in a gap region between adjacent lenses, and an orthographic projection of each lens on the base contains an orthographic projection of a sub-pixel opening on the base.

Abstract: A light-emitting diode (LED) chip includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer that are sequentially disposed on the substrate in such order. The second semiconductor layer has a light-emitting surface that is opposite to the active layer and that is formed with a microstructure. The microstructure includes a plurality of first protrusions that are separately disposed on the light-emitting surface, and a plurality of second protrusions that are disposed on the first protrusions and on the light-emitting surface between any two adjacent ones of the first protrusions.

Abstract: A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.

Abstract: A wearable device is provided. The wearable device includes at least a housing, a circuit board, a magnetic component, and a vital sign sensor. The housing includes a bottom housing. The circuit board is disposed in the housing. The magnetic component is disposed on a side that is of the circuit board and that faces the bottom housing. The magnetic component includes an accommodation hole. The vital sign sensor is disposed in the housing. The vital sign sensor includes a light emission element and a light receive element. The light emission element and the light receive element are disposed on the side that is of the circuit board and that faces the bottom housing. The light emission element is located in the accommodation hole. The light receive element is located on an outer side that is of the magnetic component and that faces away from the light emission element.

Abstract: A frame sealing adhesive of the liquid-crystal phase shifter is disposed between two transparent substrates, the frame sealing adhesive encloses a first cavity, a first part of the metal-trace layer is located inside the first cavity, and a second part of the metal-trace layer is located outside the first cavity. The second part is disposed on first surfaces or second surfaces of the two transparent substrates. If the second part is disposed on the first surfaces of the two transparent substrates, metal cushion layers are provided between the frame sealing adhesive and the first surfaces of the two transparent substrates. If the second part is disposed on the second surfaces of the two transparent substrates, the first part and the second part are electrically connected by metal via holes provided in the transparent substrates, and the frame sealing adhesive contacts the first surfaces of the two transparent substrates.

Abstract: Managing thermal capabilities of an information handling system, including identifying a maximum supported ambient temperature of the information handling system; identifying a current ambient temperature of the information handling system; calculating a temperature delta based on the maximum supported ambient temperature of the information handling system and the current ambient temperature of the information handling system; adjusting, based on the temperature delta, one or more thermal control trigger points; adjusting, based on the adjusted thermal control trigger points, a fan speed of a fan of the information handling system; and determining, based on the adjusted fan speed of the fan, an updated cooling capacity associated with the information handling system.