Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer haying a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

Abstract: A heat dissipation unit includes a heat pipe and a base seat. The base seat has a first side and a second side. The second side is formed with a channel and multiple perforations in communication with the first and second sides. The heat pipe has a heat absorption section and a conduction section. The conduction section extends from the heat absorption section in a direction to at least one end of the heat pipe distal from the heat absorption section. Several parts of the heat pipe corresponding to the perforations are received in the perforations and flush with the first side of the base seat. The heat dissipation unit improves the shortcoming of the conventional heat dissipation component that the coplanar precision between the heat pipe and the protruding platform of the base seat is hard to control.

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material.

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.

Abstract: A locating unit with a base seat locating structure. The base seat locating structure includes a base seat and a locating unit. The base seat has a pair of locating holes each having a first locating hole section and a second locating hole section and a connection section connected therebetween. The second locating hole section has a locating recess. The locating unit has a main body having a first side and a second side and a through hole passing through the main body between the first and second sides. A first protruding key and a second protruding key protrude from the second side beside the through hole. The first and second protruding keys are displaceably assembled and connected with the locating holes. Free ends of the first and second protruding keys respectively have a first end section and a second end section connected and assembled with the locating recesses.

Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.

Abstract: A fixing structure for heat dissipation assembly includes a base and multiple female fastener holders. The base has at least one through bore axially extending through an upper and a lower surface thereof, as well as coupling holes located outside the through bore and respectively having an engaging element disposed therein. The female fastener holder has a lower side formed with coupling protrusions corresponding to the coupling holes. The coupling protrusion has a guiding groove radially provided thereon and having a lower and an upper end recess for engaging with the engaging element in the corresponding coupling hole. The engaging elements in the coupling holes are guided by the guiding grooves to move from the lower to the upper recesses when the female fastener holder is turned relative to the through bore and the coupling holes on the base, bringing the coupling protrusions to axially insert into the coupling holes.

Abstract: A thermal module assembling structure includes a heat dissipation board and at least one heat pipe. The heat dissipation board has a receiving channel for fitting the heat pipe therethrough. Two sides of upper side of the receiving channel are respectively formed with two ribs. The ribs horizontally protrude and extend toward the middle of the receiving channel to face the heat pipe fitted in the receiving channel. At least one deformed recess is formed on an upper surface of each of the ribs, whereby the lower surfaces of the ribs and a surface of the heat pipe are deformed to form at least one deformed connection section between the lower surfaces of the ribs and the surface of the heat pipe. By means of the restriction of the deformed connection section, the heat pipe is prevented from being extracted out of the receiving channel.

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.

Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.

Abstract: A vehicle includes a fender, a storage compartment, and a first retaining wall. The fender has an inner surface, an outer surface, and a through hole connecting the inner surface and the outer surface. The storage compartment has a bottom plate. The bottom plate of the storage compartment is located at a side of the outer surface of the fender and at least covers the through hole. The fender is located below the storage compartment in a top-bottom direction of the vehicle. The first retaining wall is disposed on the outer surface of the fender and surrounds at least a portion of the through. A portion of the first retaining wall is closer to a front of the vehicle than the through hole in a front-rear direction of the vehicle.

Abstract: A post CMP cleaning apparatus is provided. The post CMP cleaning apparatus includes a cleaning stage. The post CMP cleaning apparatus also includes a rotating platen disposed in the cleaning stage, and the rotating platen is configured to hold and rotate a semiconductor wafer. The post CMP cleaning apparatus further includes a vibrating device disposed over the rotating platen. The post CMP cleaning apparatus further includes a solution delivery module disposed near the vibrating device and configured to deliver a cleaning fluid to the semiconductor wafer. The vibrating device is configured to provide the cleaning fluid with a specific frequency which is at least greater than 100 MHz while the rotating platen is rotating the semiconductor wafer, so that particles on the semiconductor wafer are removed by the cleaning fluid.

Abstract: A securing unit and a base seat securing structure. The base seat securing structure includes a base seat and multiple securing units. The base seat has a top side, a bottom side, multiple perforations and multiple securing holes formed through the base seat between the top side and the bottom side. The securing holes are positioned around the perforations. Each securing unit has a seat section disposed on the top side of the base seat and multiple connection sections. The seat section has a bore in communication with and corresponding to the perforation. The connection sections are disposed under a lower side of the seat section. One end of each connection section has one or multiple stopper end sections. The stopper end sections are passed through the corresponding securing holes to abut against the bottom side of the base seat.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

Abstract: A temperature measurement system for determining a performance of a smoke generating device includes a temperature measuring device. The temperature measuring device includes an elongated carrier and a number of thermal sensors disposed within the elongated carrier. The elongated carrier is configured to be inserted into an elongated chamber of the smoke generating device. Each of the thermal sensors includes a sensing end exposed on an outer surface of the elongated carrier. When the elongated carrier is inserted into the elongated chamber, the sensing ends respectively detect a temperature of a number of heating members of the smoke generating device.

Abstract: The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.