Patents by Inventor Huang Lin

Huang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER
    Publication number: 20220310457
    Abstract: A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.
    Type: Application
    Filed: November 23, 2021
    Publication date: September 29, 2022
    Inventors: Huiching Chang, I-Ming Chang, Huang-Lin Chao
  • FERROELECTRIC MEMORY CELL
    Publication number: 20220310638
    Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.
    Inventors: Chung-Liang CHENG, Huang-Lin CHAO
  • Protective Liner for Source/Drain Contact to Prevent Electrical Bridging While Minimizing Resistance
    Publication number: 20220278211
    Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Kuo-Chiang Tsai, Hsin-Huang Lin, Jyh-Huei Chen
  • METHOD FOR FORMING EPITAXIAL SOURCE/DRAIN FEATURES USING A SELF-ALIGNED MASK AND SEMICONDUCTOR DEVICES FABRICATED THEREOF
    Publication number: 20220278002
    Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Yao-Sheng Huang, I-MING CHANG, Huang-Lin Chao
  • CONTACT STRUCTURES IN SEMICONDUCTOR DEVICES
    Publication number: 20220254684
    Abstract: A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.
    Type: Application
    Filed: November 4, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Soon LIM, Chung-Liang Cheng, Huang-Lin Chao
  • GATE CONTACT AND VIA STRUCTURES IN SEMICONDUCTOR DEVICES
    Publication number: 20220254927
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.
    Type: Application
    Filed: September 9, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Sheng-Tsung Wang, Huang-Lin Chao
  • Vapor chamber structure
    Patent number: 11397057
    Abstract: A vapor chamber structure includes a main body. The main body has a chamber. The chamber has a first side, a second side and a connection body. Two axial ends of the connection body are respectively connected with the first and second sides. A first capillary structure layer is disposed around the connection body along a periphery thereof. A working fluid is filled in the chamber. The connection body serves to prevent the main body from deforming when heated and enhance the heat conduction efficiency.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 26, 2022
    Inventor: Sheng-Huang Lin
  • Methods to compress, encrypt and retrieve genomic alignment data
    Patent number: 11393559
    Abstract: A genomic data decoder may jointly compress and encrypt genomic data alignment information while preserving the privacy of sensitive genomic data elements at retrieval stage. Genomic data alignment information organized as a read-based alignment data stream may be transposed into a position-based alignment data stream. The position-based alignment information may been coded into a reference-based alignment data stream. The reference-based alignment data stream may be encrypted with a combination of order-preserving encryption of the genomic position information and symmetric encryption of the reference-based alignment differential data. Differential encoding and entropy coding schemes may further compress the reference-based alignment data stream. The resulting compressed and encrypted stream may be indexed and stored in a biobank storage unit.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 19, 2022
    Assignee: SOPHIA GENETICS S.A.
    Inventors: Adam Molyneaux, Erman Ayday, Jean-Pierre Hubaux, Jesus Garcia, Zhicong Huang, Huang Lin
  • CHEMICAL MECHANICAL POLISHING SLURRY COMPOSITION AND METHOD OF POLISHING METAL LAYER
    Publication number: 20220195246
    Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 23, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Liao, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Huang-Lin Chao
  • INDOLINE DERIVATIVES FOR TREATMENT AND/OR PREVENTION OF FIBROSIS DISEASES
    Publication number: 20220184032
    Abstract: The invention relates to the use of Indoline derivatives, and their effective dose in the prevention and/or treatment of fibrosis diseases. The compound can effectively prevent and/or treat a fibrosis disease without cytotoxicity or genotoxicity.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Chien Huang LIN, Jing-Ping LIOU, Shiow-Lin PAN, Che-Ming TENG
  • Method and system for processing building information modeling data
    Patent number: 11361120
    Abstract: The present invention relates to a method for processing building information modeling data including the following steps: inputting a building information model's data that includes two types of multiple objects; identifying the objects to generate results of identification; dividing the objects into a first category and a second category in accordance with the results of identification; removing the objects of the second category; readjusting the first category of objects in accordance with a predetermined rule of a building energy simulation software; and defining attributes of the objects of the first category.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: June 14, 2022
    Assignee: RUENTEX ENGINEERING & CONSTRUCTION CO., LTD.
    Inventors: Samuel Yin, Wu-Sung Chen, Jui-Chen Wang, Ming-Huang Lin, Wen-Kuei Chang
  • Tuning Threshold Voltage in Field-Effect Transistors
    Publication number: 20220181467
    Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Inventors: Hsueh Wen Tsau, Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung
  • Fender assembly and vehicle including thereof
    Patent number: 11338875
    Abstract: A vehicle includes a fender, a storage compartment, and a first retaining wall. The fender has an inner surface, an outer surface, and a through hole connecting the inner surface and the outer surface. The storage compartment has a bottom plate. The bottom plate of the storage compartment is located at a side of the outer surface of the fender and at least covers the through hole. The fender is located below the storage compartment in a top-bottom direction of the vehicle. The first retaining wall is disposed on the outer surface of the fender and surrounds at least a portion of the through. A portion of the first retaining wall is closer to a front of the vehicle than the through hole in a front-rear direction of the vehicle.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: May 24, 2022
    Assignee: Gogoro Inc.
    Inventors: Hsiu-Huang Lin, Chia-Hao Chang
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20220157653
    Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a source/drain structure formed beside the gate structure. The structure also includes a contact structure formed over the source/drain structure. The structure also includes a dielectric structure extending into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung LIAO, Lin-Yu HUANG, Chia-Hao CHANG, Huang-Lin CHAO
  • HEAT DISSIPATION DEVICE WITH MULTIPLE HEAT DISSIPATION ZONES
    Publication number: 20220141994
    Abstract: A heat dissipation device includes a base having a first surface in contact with at least one heat source and an opposite second surface having a heat dissipation zone upward extended therefrom; an auxiliary heat dissipation zone horizontally extended from one of four lateral sides or directions of the heat dissipation zone; an air guiding section defined at the auxiliary heat dissipation zone; and at least one upward indented zone formed between the auxiliary heat dissipation zone and the side of the heat dissipation zone having the auxiliary heat dissipation zone sideward sidewardly extended from a higher portion thereof. With these arrangements, the heat dissipation device can guide air flow currents directly or indirectly to a plurality of heat sources located corresponding to the heat dissipation zone and the auxiliary heat dissipation zone at the same time to cool them.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 5, 2022
    Inventors: Sheng-Huang Lin, Yen-Lin Chu
  • Base fastener
    Patent number: 11313396
    Abstract: The present invention relates to a base fastener which is disposed corresponding to a pair of arc holes on a base. The base fastener comprises a body. The body has a first side, a second side, and a throughhole. The throughhole penetrates through the first side and the second side. A first post and a second post protrude from the second side beside the throughhole. The first post, the second post, and the pair of arc holes are disposed correspondingly and rotatably connected to each other to be assembled with the base firmly.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 26, 2022
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventor: Sheng-Huang Lin
  • Light projection device and electronic device using same
    Patent number: 11287734
    Abstract: A single light projection device providing illumination in two opposing directions includes a lens module and a light source module. The lens module includes a light-incident surface, a first light-emitting surface, and a second light-emitting surface. The light source module includes a light source configured for emitting light toward the light-incident surface. The first light-emitting surface and the second light-emitting surface introduce the light from the light source module outside of the light projection device in two different and opposing directions.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 29, 2022
    Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.
    Inventors: Wei-Wei Qi, Ching-Huang Lin
  • Indoline derivatives for treatment and/or prevention of fibrosis diseases
    Patent number: 11278523
    Abstract: The invention relates to the use of Indoline derivatives, and their effective dose in the prevention and/or treatment of fibrosis diseases. The compound can effectively prevent and/or treat a fibrosis disease without cytotoxicity or genotoxicity.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 22, 2022
    Assignee: Taipei Medical University
    Inventors: Chien Huang Lin, Jing-Ping Liou, Shiow-Lin Pan, Che-Ming Teng
  • WORK FUNCTION LAYERS FOR TRANSISTOR GATE ELECTRODES
    Publication number: 20220077296
    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang CHENG, Ziwei FANG, Chun-I WU, Huang-Lin CHAO
  • Chemical mechanical polishing slurry composition and method of polishing metal layer
    Patent number: 11267987
    Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Liao, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Huang-Lin Chao