Abstract: A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.

Abstract: A method for preparing a heat-moisture-resistant polyurethane elastomer includes (A) providing a polyol and an aliphatic diisocyanate to react in the presence of a suitable catalyst under a heating environment, thereby forming a urethane prepolymer with an reactive isocyanate terminal group; (B) providing a hydrophobic diol with a hydroxyl group and/or a castor oil-based triol as a chain extender; and (C) performing an addition reaction of the urethane prepolymer and the chain extender under an appropriate heating environment to generate the heat-moisture-resistant polyurethane elastomer that can be used for a long time in a warm and humid environment.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: A mechanism is provided for automatically detecting, diagnosing, transporting, and repairing devices having failed during burn-in testing. Embodiments provide a system that monitors devices undergoing burn-in testing and detecting when a device or a component within a device fails the burn-in test. Embodiments can then alert burn-in-rack monitor personnel of the device failure. Embodiments can concurrently determine the nature of the failure applying a machine learning-based prediction model against log files associated with the failed device. The diagnosis along with a recommended repair strategy can be provided to the repair center as an aid in accelerating the repair process. In addition, the diagnosis can be used to order parts for the repair from a parts depot. In this manner, embodiments can reduce the time for detection, diagnosis, and repair of the failed device.

Abstract: A touch reading system for playing cloud-based audio and video contents through application software (APP) includes a book with an invisible printed code and a touch reading pen with a wireless transmission function. The touch reading pen can obtain a digital number from the book and transmit the digital number to a smart device with APP supported by an arbitrary one of the existing operating systems. The touch reading system allows audio and video contents to be played by devices other than a displaying device, and can connect to a cloud server through the networking function of the smart device so that the desired video contents can be easily downloaded, updated, and managed through the APP to increase the videos available to be played. The touch reading system adopts a cross-platform APP system and supports all the currently mainstream operating systems such as Android, Windows, and iOS.

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A dual heat transfer structure, comprising: at least a heat pipe and at least a vapor chamber; the heat pipe having a first end, an extension portion, and a second end, the first and second ends disposed at the two ends of the extension portion; the vapor chamber being concavely bent with its two ends being joined together and selectively compasses, encircles, encloses, or surrounds one of the first and second ends and extension portion. The dual heat transfer structure of the present invention is a complex structure that can both transfer heat with a large area and to the distal end of the structure.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: A heat sink device, comprising a body, at least a heat pipe, and a base. The body has a first side and a second side onto which a heat source is attached. The heat pipe has a heat-absorbing portion and a heat-dissipating portion. The heat-absorbing portion is attached to the first side, while the heat-dissipating portion is away from the heat-absorbing portion, so that the heat generated by the heat source is absorbed by the heat-absorbing portion and transferred to the distal end of the heat-dissipating portion. The base is disposed on the heat pipe and above the body.

Abstract: A method of checking file data is provided. The method includes obtaining text information of a test file. The text information of the test file is converted into vectors, thus vectors corresponding to the test file are obtained. A quality category of the test file is obtained based on the vectors corresponding to the test file. Once the test file is determined not to meet a requirement according to the quality category of the test file, a template file corresponding to the test file is provided.

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

Abstract: A vapor chamber structure includes a main body. The main body has a first section, a second section, a capillary structure and a working fluid. The first section has a first chamber. The second section has a second chamber. The second section extends from one end of the first section in a direction away from the first section. The capillary structure is disposed on inner surfaces of the first and second chambers. The working fluid is filled in the first and second chambers. The vapor chamber structure has both heat spreading effect and remote end heat dissipation effect.

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.

Abstract: An always-on system with multi-layer power management includes an always-on portion that is powered in shutdown state and all power states while rest portions of the system are not powered in the shutdown state; a memory unit that is powered in sleep state to retain data in the memory unit; an input interface that is powered only in event detection state, in which at least one captured image is received from an image sensor, the event detection state beginning when a trigger signal is issued; an event monitor that detects motion in the captured image; a digital signal processor (DSP) that is powered only in computer vision state to perform image identification on the captured image if motion is detected; and an output interface is powered only in the computer vision state, a result of the DSP being outputted via the output interface.