Abstract: A system for measuring a satellite ghost efficiency of a diffractive lens is provided. The system includes a light source configured to output a first probing beam, and a beam tweaking assembly disposed between the light source and the diffractive lens, and configured to convert the first probing beam into a second probing beam that is a non-collimated beam. The diffractive lens diffracts the second probing beam into a plurality of diffracted beams including a first diffracted beam of a parent diffraction order and a second diffracted beam of a satellite ghost diffraction order. The beam tweaking assembly includes one or more optical lenses, and an adjustable optical power. The system also includes a detector configured to generate a beam spot pattern including a first beam spot corresponding to the first diffracted beam and a second beam spot corresponding to the second diffracted beam.

Abstract: The present application provides a processing method of a metal composite structure including a first metal layer and a second metal layer stacked on the first metal layer. The processing method includes the steps of defining a first through hole in the first metal layer, and drilling in the first through hole toward the second metal layer to form a traction hole in the second metal layer. Then, hot melt drilling is performed on a surface of the second metal layer away from the first metal layer toward the first through hole, thereby causing the second metal layer to crack under a traction force of the traction hole to form a second through hole, and a portion of the second metal layer to be melted and squeezed to form a bushing which adheres to at least a portion of a sidewall of the first through hole.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: A transmission device for multi-frequency equal-amplitude non-harmonic electrical prospecting signal includes a single-chip microcontroller, a field programmable gate array (FPGA), a digital to analog conversion (DAC) module, an isolation amplifier circuit, a differential amplifier module, a digital power amplifier circuit, and a sensor module connected successively. A plurality of output ends of the digital power amplifier circuit is in cascade connection with a grounding electrode A and a grounding electrode B to form a loop with ground. An input end of the sensor module is connected with the digital power amplifier circuit. An output end of the sensor module is connected with the single-chip microcontroller.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: A method for preparing bismuth oxide nanowire films by heating in an upside down position includes: washing a substrate, and fixing the substrate to a substrate support in a magnetron sputtering system in a position where an electrically conductive surface of the substrate faces downwards; placing a bismuth target, which is adhered to a copper backing plate, on a sputtering head in the magnetron sputtering system; performing direct current magnetron sputtering to form a bismuth film on the electrically conductive surface of the substrate; and regulating a heating temperature to maintain the bismuth film in a semi-molten state, and providing a predetermined oxygen gas concentration to form the bismuth oxide nanowire film.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.

Abstract: A device and method for measuring spectrum parameters of a formation outcrop and a rock mass are provided. An excitation signal is generated by a direct digital synthesis (DDS) module of a signal transmission portion. A constant voltage mode or a constant current mode is adopted for observation. After the signal passes through a constant voltage/constant current module, a constant high-voltage signal source or a current source signal with constant current output is formed and output to ground through grounding electrodes A and B to establish a stable observation signal field source. Geoelectric response information under the excitation of each frequency signal is acquired by a signal receiving portion through grounding electrodes M and N, processed and send out to a microcontroller unit (MCU) for display and storage. The spectrum parameters at different depths are observed by adjusting geometric dimensions of AB and MN.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: A semiconductor package includes a first semiconductor die, an adhesive layer, a second semiconductor die, a plurality of conductive pillars and an encapsulant. The adhesive layer is adhered to the first semiconductor die. The second semiconductor die is stacked over the first semiconductor die. The conductive pillars surround the first semiconductor die. The encapsulant encapsulates the first semiconductor die and the conductive pillars, wherein a top surface of the encapsulant is higher than top surfaces of the conductive pillars.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.

Abstract: One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

Abstract: A package structure including a packaging substrate, a semiconductor device, passive components, a lid, and a dam structure is provided. The semiconductor device is disposed on and electrically connected to the packaging substrate. The passive components are disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components. The lid is disposed on the packaging substrate, and the lid covers the semiconductor device and the passive components. The dam structure is disposed between the packaging substrate and the lid, wherein the dam structure covers the passive components and laterally encloses the semiconductor device.

Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.

Abstract: There is disclosed a method of operating a transmitting node in a millimeter-wave communication network. The method includes transmitting millimeter-wave signaling in a transmission timing structure, the transmission timing structure including N time interval elements sequentially ordered in time, the millimeter-wave signaling including N separate signaling structures, each signaling structure being transmitted in a different one of the time interval elements. N is an integer multiple of 2. A first subset of the N separate signaling structures corresponds to control signaling, the subset including 2{circumflex over (?)}m signaling structures consecutive in time beginning with the signaling structure of the first time interval element, and m is an integer such that 2{circumflex over (?)}m<=N. A second subset of the N separate signaling structures corresponds to data signaling, the second subset comprising 0 or an integer number of signaling structures.

Abstract: An electrolyte composition comprising a fluoroamino solvent and a lithium salt comprised of boron dissolved in the fluoroamino solvent, the fluoroamino solvent being a fluoroacetamide or fluoroimide may be used as an electrolyte in a secondary battery. The electrolyte composition is useful for lithium ion batteries having an anode comprised of lithium metal and the electrolyte may be present in a lean amount.