Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.

Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.

Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.

Abstract: An embodiment thermal interface material may include a first component including a first thermal conductivity that is between 20 W/cm·K and 30 W/cm·K and a second component including a second thermal conductivity that is between 30 W/cm·K and 40 W/cm·K. Each of the first component and the second component may include a thermally conductive material including one or more of graphite, graphene, carbon nanotubes, a metal, and a phase change material. For example, each of the first component and the second component include graphite dispersed within a polymer matrix that may include one or more of a hydrogenated hydrocarbon resin, polybutene, polyisobutylene, and an acrylic acid ester copolymer. According to an embodiment, the first component may include 40 wt % to 60 wt % graphite and the second component may include 60 wt % to 70 wt % graphite.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: An IC device includes a gate electrode extending along a first direction, a channel extending through the gate electrode in a second direction perpendicular to the first direction and positioned at a first elevation along a third direction perpendicular to each to the first and second directions, an isolation layer positioned within the gate electrode at a second elevation different from the first elevation, first and second source/drain (S/D) structures adjacent to the channel and positioned on opposite sides of the gate electrode at the first elevation, third and fourth S/D structures positioned on opposite sides of the gate electrode at the second elevation, and a conductive structure extending in the second direction and electrically connected to each of the third and fourth S/D structures.

Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

Abstract: A semiconductor device includes an area including cell regions arranged in alternating first and second rows extending in a first direction, relative to a second direction substantially perpendicular to the first direction, the first rows having a first height, and the second rows having a second height different from the first height; a majority of the cell regions having the first height; a minority of the cell regions having a third height that is at least a sum of the first height and the second height; and for first and second types of cell regions, the first type of cell region having the first height and the second type of cell region having the third height, the first type of cell region having a width greater than a width of the second type of cell region.

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.

Abstract: A computer-implemented method may include (1) causing a radar component to emit one or more radar signals and (2) causing the radar component to analyze one or more return signals. Also disclosed is a method for forming a 3D liquid crystal polarization hologram optical element and a method for characterizing diffractive waveguides includes directing light onto a structure and measuring the diffracted light to capture at least one image of the structure. Lastly, disclosed is a method of pattering organic solid crystals and a method directing a beam of input light to a surface of an optical material to determine crystallographic and optical parameters of the optical material. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: This document describes systems and techniques directed at a machine-learning-based greedy optimization mechanism for reducing radio-frequency (RF) tests in production. In aspects, a process capability index is disclosed, the process capability index used to refine a test-set. The test-set includes tests configured to be performed on an electronic device. The process capability index is configured based on upper specification limits and lower specification limits of the electronic device for each test in the test-set, as well as results for each of the tests in the test-set. The process capability index is further configured based on a new upper specification limit and a new lower specification limit of the electronic device for a new test not in the test-set, as well as results for the new test.

Abstract: A device is provided. The device includes a light guide configured to guide a first light propagating therein. The device also includes an optical film coupled with the light guide, optically anisotropic molecules in the optical film being configured with an in-plane orientation pattern having an in-plane pitch along the predetermined in-plane direction. Within the in-plane pitch of the in-plane orientation pattern, azimuthal angles of the optically anisotropic molecules are configured to vary nonlinearly along the predetermined in-plane direction. The optical film is configured to diffract the first light as a plurality of second lights at a plurality of locations of the optical film, with a plurality of predetermined, different diffraction efficiencies.