Abstract: A manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.

Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Abstract: A ribbon speaker includes a housing, first and second magnet assemblies, a ribbon diaphragm, a coil, and a flexible substrate. The first and second magnet assemblies is arranged in the housing. The same poles of the first magnet assembly and the second magnet assembly are arranged opposite to each other. The diaphragm is positioned between these magnet assemblies. The coil, placed on this diaphragm, includes two first connection portions. The flexible substrate includes a body, two connection portions, and two soldering portions. The body's first part is inside the housing, while the second part arranged outside. The second connections on the body's first part electrically connected to the coil's first connections. The externally positioned soldering portions facilitate easier assembly, significantly reducing soldering complexity. The soldering portions are respectively and electrically connected to the second connection portions.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: Various embodiments include integrated circuit packages and methods of forming integrated circuit packages. In an embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a stiffener ring around the integrated circuit device and attached to the package substrate; a lid attached to the stiffener ring; a channel connected to an area between the lid and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top-down view; and a thermal interface material in the channel and in the area between the lid and the integrated circuit device.

Abstract: A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. The second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. The third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.

Abstract: A package structure includes a package substrate, an interposer module on the package substrate, a thermal interface material (TIM) layer on the interposer module, and a package lid on the TIM layer, including a package lid foot portion attached to the package substrate, a package lid plate portion connected to the package lid foot portion, and a plurality of fins extending from the package lid plate portion into the TIM layer over the interposer module.

Abstract: A system for measuring a satellite ghost efficiency of a diffractive lens is provided. The system includes a light source configured to output a first probing beam, and a beam tweaking assembly disposed between the light source and the diffractive lens, and configured to convert the first probing beam into a second probing beam that is a non-collimated beam. The diffractive lens diffracts the second probing beam into a plurality of diffracted beams including a first diffracted beam of a parent diffraction order and a second diffracted beam of a satellite ghost diffraction order. The beam tweaking assembly includes one or more optical lenses, and an adjustable optical power. The system also includes a detector configured to generate a beam spot pattern including a first beam spot corresponding to the first diffracted beam and a second beam spot corresponding to the second diffracted beam.

Abstract: A transmission device for multi-frequency equal-amplitude non-harmonic electrical prospecting signal includes a single-chip microcontroller, a field programmable gate array (FPGA), a digital to analog conversion (DAC) module, an isolation amplifier circuit, a differential amplifier module, a digital power amplifier circuit, and a sensor module connected successively. A plurality of output ends of the digital power amplifier circuit is in cascade connection with a grounding electrode A and a grounding electrode B to form a loop with ground. An input end of the sensor module is connected with the digital power amplifier circuit. An output end of the sensor module is connected with the single-chip microcontroller.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: A method for preparing bismuth oxide nanowire films by heating in an upside down position includes: washing a substrate, and fixing the substrate to a substrate support in a magnetron sputtering system in a position where an electrically conductive surface of the substrate faces downwards; placing a bismuth target, which is adhered to a copper backing plate, on a sputtering head in the magnetron sputtering system; performing direct current magnetron sputtering to form a bismuth film on the electrically conductive surface of the substrate; and regulating a heating temperature to maintain the bismuth film in a semi-molten state, and providing a predetermined oxygen gas concentration to form the bismuth oxide nanowire film.

Abstract: A device and method for measuring spectrum parameters of a formation outcrop and a rock mass are provided. An excitation signal is generated by a direct digital synthesis (DDS) module of a signal transmission portion. A constant voltage mode or a constant current mode is adopted for observation. After the signal passes through a constant voltage/constant current module, a constant high-voltage signal source or a current source signal with constant current output is formed and output to ground through grounding electrodes A and B to establish a stable observation signal field source. Geoelectric response information under the excitation of each frequency signal is acquired by a signal receiving portion through grounding electrodes M and N, processed and send out to a microcontroller unit (MCU) for display and storage. The spectrum parameters at different depths are observed by adjusting geometric dimensions of AB and MN.

Abstract: A semiconductor package includes a first semiconductor die, an adhesive layer, a second semiconductor die, a plurality of conductive pillars and an encapsulant. The adhesive layer is adhered to the first semiconductor die. The second semiconductor die is stacked over the first semiconductor die. The conductive pillars surround the first semiconductor die. The encapsulant encapsulates the first semiconductor die and the conductive pillars, wherein a top surface of the encapsulant is higher than top surfaces of the conductive pillars.

Abstract: A package structure including a packaging substrate, a semiconductor device, passive components, a lid, and a dam structure is provided. The semiconductor device is disposed on and electrically connected to the packaging substrate. The passive components are disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components. The lid is disposed on the packaging substrate, and the lid covers the semiconductor device and the passive components. The dam structure is disposed between the packaging substrate and the lid, wherein the dam structure covers the passive components and laterally encloses the semiconductor device.

Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.

Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.

Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.