Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first redistribution structure, a packaged device and a second redistribution structure. The packaged device is on a first side of the first redistribution structure and the second redistribution structure is on a second side of the first redistribution structure. An encapsulant is on the second side of the first redistribution structure and laterally around the second redistribution structure, wherein the encapsulant covers a periphery of the second redistribution structure such that an uncovered surface of the second redistribution structure is defined.

Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: A multiport USB-PD adaptor including a flyback-converter, a USB controller including a USB-PD subsystem and buck-controller, and multiple buck and bypass-circuits, and methods for operating the same are provided. Generally, the adaptor is operated in a buck-bypass-mode, in which at least one buck-circuit is bypassed and the flyback-converter is operated to generate an input voltage (VIN) to the buck-circuits equal to a requested output voltage (VOUT_C), which is then coupled directly to the associated port. Buck-circuits coupled to other active ports can also be bypassed if the requested VOUT_Cs are the same, or the buck-circuits operated to provide another VOUT_C. If a bypass-circuit unavailable, the adaptor is operated in a variable-buck-input-mode by determining a highest VOUT_C requested on any port and setting VIN to a sum of the highest VOUT_C and an offset voltage. Buck-circuits coupled to active ports are then operated to provide the requested output voltages.

Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

Abstract: A device includes a polarization non-selective partial reflector configured to transmit a first portion of a first light and reflect a second portion of the first light. The device also includes a polarization selective reflector configured to reflect the first portion of the first light received from the polarization non-selective reflector back to the polarization non-selective reflector. The device further includes a path correction device disposed between the polarization non-selective partial reflector and the polarization selective reflector, and configured to forwardly steer the first portion of the first light propagating between the polarization non-selective partial reflector and the polarization selective reflector.

Abstract: A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: A method for synthesizing an intergrown twin Ni2Mo6S6O2/MoS2 two-dimensional nanosheet with exposed (00L) crystal planes is disclosed. An Ni-Mo bonded precursor is formed by using an ion insertion method to restrict Ni ions to be located in a lattice matrix of a Mo-based compound; a dinuclear metal sulfide Ni2Mo6S6O2 is formed by precisely adjusting and controlling a concentration of a sulfur atmosphere and utilizing a reconstruction effect of Ni element in the lattice matrix of the Mo-based compound; and meanwhile, a growth direction of Ni2Mo6S6O2 is precisely adjusted and controlled by using a method for growing a single crystal in a limited area, so that Ni2Mo6S6O2 is grown, taking a single crystal MoS2 as a growth template, with the single crystal MoS2 alternately along a crystal plane (110) of the single crystal MoS2, so as to form a twin Ni2Mo6S6O2/MoS2 two-dimensional nanosheet in which Ni2Mo6S6O2and MoS2 are intergrown.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: A polarization modulator includes a first liquid crystal cell and a second liquid crystal cell. The first liquid crystal cell has a first type of liquid crystals configured to rotate an optical axis of light parallel to a first plane of the first liquid crystal cell. The second liquid crystal cell is configured to receive the light from the first liquid crystal cell. The second liquid crystal cell has a second type of liquid crystals configured to rotate the optical axis of the light perpendicular to a second plane of the second liquid crystal cell.

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.