Patents by Inventor Hui Cheng

Hui Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996345
    Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11973005
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11965833
    Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: April 23, 2024
    Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jing-Zhi Hou, Lin-Hui Cheng, Yan-Chao Ma, Jin-Cai Zhou, Zi-Long Ma, Neng-Neng Zhang, Yi Chen, Chen-Xi Tang, Meng Lu, Peng Zhou, Ling-Hui Zhang, Lu-Hui Fan, Shi-Gang Xu, Cheng-Yi Chao, Liang-Yi Lu
  • Patent number: 11959960
    Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Hui Cheng, Chia-Jung Chang
  • Patent number: 11954020
    Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: April 9, 2024
    Assignee: Hefei Core Storage Electronics Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Xu Hui Cheng
  • Patent number: 11953796
    Abstract: A device is provided. The device includes a first Pancharatnam-Berry phase (“PBP”) lens, and a second PBP lens stacked with the first PBP lens. Each of the first PBP lens and the second PBP lens includes a liquid crystal (“LC”) layer. Each side of the LC layer is provided with a continuous electrode and a plurality of patterned electrodes. The patterned electrodes in the first PBP lens are arranged non-parallel to the patterned electrodes in the second PBP lens.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Lu Lu, Xiayu Feng, Hsien-Hui Cheng
  • Patent number: 11946161
    Abstract: A method for synthesizing an intergrown twin Ni2Mo6S6O2/MoS2 two-dimensional nanosheet with exposed (00L) crystal planes is disclosed. An Ni—Mo bonded precursor is formed by using an ion insertion method to restrict Ni ions to be located in a lattice matrix of a Mo-based compound; a dinuclear metal sulfide Ni2Mo6S6O2 is formed by precisely adjusting and controlling a concentration of a sulfur atmosphere and utilizing a reconstruction effect of Ni element in the lattice matrix of the Mo-based compound; and meanwhile, a growth direction of Ni2Mo6S6O2 is precisely adjusted and controlled by using a method for growing a single crystal in a limited area, so that Ni2Mo6S6O2 is grown, taking a single crystal MoS2 as a growth template, with the single crystal MoS2 alternately along a crystal plane (110) of the single crystal MoS2, so as to form a twin Ni2Mo6S6O2/MoS2 two-dimensional nanosheet in which Ni2Mo6S6O2 and MoS2 are intergrown.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 2, 2024
    Assignee: Institute of Analysis, Guangdong Academy of Sciences (China National Analytical Center, Guangzhou)
    Inventors: Fuxian Wang, Hui Cheng, Liling Wei, Qiong Liu
  • Publication number: 20240103194
    Abstract: A detection device for high-frequency pseudo-random spread spectrum coded sequence signal of shallow geologic body includes a signal transmitter and a synchronous signal receiver. The signal transmitter includes a first Mono-Chip Computer (MCU), a first Field Programmable Gate Array (FPGA), a power amplifier module, a direct-current (DC) power supply, a first display module, a first Global Position System (GPS) synchronization module, a first communication module, and a first memory module. The synchronous signal receiver includes a preamplifier circuit, a bandpass filter circuit, a program-controlled amplifier circuit, an analog to digital (AD) converter circuit, a second FPGA, a second MCU, a second communication module, a second display module, a second GPS synchronization module, and a second memory module. A method using the detection device is further provided.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventors: Hui CHENG, Chenxing JIA, Diquan LI, Guohong FU, Xiuying LIAO
  • Patent number: 11939688
    Abstract: Photoelectrochemical (PEC) technology for the conversion of solar energy into chemicals may require cost-effective photoelectrodes to efficiently and stably drive anodic and/or cathodic half-reactions to complete the overall reactions for storing solar energy in chemical bonds. Apparatus and systems incorporating effectively transparent metal catalysts enable the design and/or implementation of PEC devices for light harvesting. Triple-junction photocathodes with the triangular catalyst grids are provided to improve the efficiency of the photocathodes to generate renewable fuel from sunlight.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 26, 2024
    Assignee: California Institute of Technology
    Inventors: Wen-Hui Cheng, Harry A. Atwater, Rebecca Saive, Matthias H. Richter, Sisir Yalamanchili, Michael D. Kelzenberg, Kelly McKenzie
  • Patent number: 11942403
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20240096732
    Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.
    Type: Application
    Filed: January 13, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Hao CHEN, Li-Hui CHENG, Ying-Ching SHIH
  • Publication number: 20240079399
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11923259
    Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
  • Publication number: 20240069693
    Abstract: A method for sharing a console variable setting of an application and the electronic device and system is provided. The sharing method includes: capturing a display frame of a first electronic device to obtain a set coding image by a second electronic device; transforming the set coding image into a meta file by the second electronic device, wherein the meta file comprises a set of setting parameters for a plurality of first setting options of a first application of the first electronic device; and setting a plurality of second setting options of a second application of the second electronic device as the set of setting parameters for the plurality of first setting options according to the meta file, wherein the second application is the same as the first application.
    Type: Application
    Filed: November 5, 2023
    Publication date: February 29, 2024
    Inventors: Chun-Yu KUO, Da-Ke LIU, Shih-Hui CHENG
  • Publication number: 20240071847
    Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20240071857
    Abstract: A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 11901255
    Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11894287
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Publication number: 20240038623
    Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Yi-Huan Liao, Pu Wang, Li-Hui Cheng
  • Publication number: 20240017388
    Abstract: The invention provides a pneumatic nail gun, comprising a gun body, a nail box, a fork and a nail forming device. The gun body comprises a sliding groove, a nail outlet adjacent to the sliding groove and a push block. The nail box and the fork are fixed on the gun body. The nail box is configured to place a plurality of strip nails to be sequentially exposed from the nail outlet. The formed fork comprises two forming surfaces with unequal heights, and the two forming surfaces are adjacent to the nail outlet. The nail forming device comprises two jaw arms, two control arms and a push seat, and the push block drives the two control arms to drive the two jaw arms to rotate and close the two forming jaws, and to drive the push seat to slide on the sliding groove.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Inventor: Hui-Cheng CHENG