Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided.

Abstract: A device includes a display element and a lens assembly. The lens assembly includes a polarization non-selective partial reflector, a polarization selective reflector and a polarization switch disposed at opposite sides of the polarization non-selective partial reflector, and a polarization selective transmissive lens disposed between the polarization switch and the polarization non-selective partial reflector. The device also includes a controller configured to: during a first sub-frame of a display frame, control the display element to display a first virtual sub-image including content of a first portion of a virtual image, and control the polarization switch to operate in a switching state. The controller is also configured to: during a second sub-frame of the display frame, control the display element to display a second virtual sub-image including content of a second portion of the virtual image, and control the polarization switch to operate in a non-switching state.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: A device includes a display element, and a lens assembly coupled with the display element. The lens assembly includes a first polarization selective reflector and a second polarization selective reflector each configured to be switchable between operating in an active state and a non-active state. The lens assembly includes a polarization non-selective partial reflector disposed between the first and second polarization selective reflectors. The device includes a controller configured to control, during a first time period, the display element to display a first virtual object, the first polarization selective reflector to operate in the active state, and the second polarization selective reflector to operate in the non-active state, and control, during a second time period, the display element to display a second virtual object, the first polarization selective reflector to operate in the non-active state, and the second polarization selective reflector to operate in the active state.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Abstract: Disclosed herein are methods of treating a tumor in a subject, including administering to the subject one or more miRNA nucleic acids or variants (such as mimics or mimetics) thereof with altered expression in the tumor. Also disclosed herein are compositions including one or more miRNA nucleic acids. In some examples, the miRNA nucleic acids are modified miRNAs, for example, and miRNA nucleic acid including one or more modified nucleotides and/or a 5?-end and/or 3?-end modification. In particular examples, the modified miRNA nucleic acid is an miR-30a nucleic acid. Further disclosed herein are methods of diagnosing a subject as having a tumor with altered expression of one or more miRNA nucleic acids. In some embodiments, the methods include detecting expression of one or more miRNAs in a sample from the subject and comparing the expression in the sample from the subject to a control.

Abstract: A device for reducing turn-off time of a transient electromagnetic transmitting signal includes a transmitting coil, a first electronic switch to control connection mode of the transmitting coil and a second electronic switch configured to form a bridge arm. The transmitting coil is a twisted pair including a first wire and a second wire. The first wire is connected to one end of the second electronic switch. The other end of the second electronic switch is connected to one end of the first electronic switch. The other end of the first electronic switch is connected to the second wire. The connection mode of the transmitting coil includes head-to-head connection, head-to-tail connection and tail-to-tail connection between the first wire and the second wire. The first wire and the second wire are connected to form a transmitting loop.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first redistribution structure, a packaged device and a second redistribution structure. The packaged device is on a first side of the first redistribution structure and the second redistribution structure is on a second side of the first redistribution structure. An encapsulant is on the second side of the first redistribution structure and laterally around the second redistribution structure, wherein the encapsulant covers a periphery of the second redistribution structure such that an uncovered surface of the second redistribution structure is defined.

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: A multiport USB-PD adaptor including a flyback-converter, a USB controller including a USB-PD subsystem and buck-controller, and multiple buck and bypass-circuits, and methods for operating the same are provided. Generally, the adaptor is operated in a buck-bypass-mode, in which at least one buck-circuit is bypassed and the flyback-converter is operated to generate an input voltage (VIN) to the buck-circuits equal to a requested output voltage (VOUT_C), which is then coupled directly to the associated port. Buck-circuits coupled to other active ports can also be bypassed if the requested VOUT_Cs are the same, or the buck-circuits operated to provide another VOUT_C. If a bypass-circuit unavailable, the adaptor is operated in a variable-buck-input-mode by determining a highest VOUT_C requested on any port and setting VIN to a sum of the highest VOUT_C and an offset voltage. Buck-circuits coupled to active ports are then operated to provide the requested output voltages.

Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

Abstract: A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.