Abstract: A power semiconductor device can include: a substrate, including an active region having a source region and a drain region each of a first doping type and extending from an upper surface of the substrate into an interior thereof; a gate trench, formed between the source region and the drain region and being recessed from the upper surface of the substrate to the active region; a main gate located in the gate trench, where the main gate extends downward from an upper surface of the gate trench; and an insulating layer, formed between an inner wall of the gate trench and the main gate.

Abstract: A curved display apparatus, includes a display panel, a backlight module, and a rear housing. The display panel and the rear housing are arranged opposite to each other in a first direction. The display panel includes a display area and a non-display area. The non-display area includes a connection portion, a first control portion, and a second control portion. The connection portion is located on the side of the first control portion away from the display area, and the second control portion is located on the side of the connection portion away from the display area. The connection portion is bendable such that the second control portion is folded to the side of the backlight module facing away from the display panel and is opposite to the first control portion, and the second control portion is connected to the backlight module.

Abstract: Provided are a high temperature-resistant composite nanofiltration membrane and a preparation method thereof. The high temperature-resistant composite nanofiltration membrane includes a base membrane and a polyamide membrane arranged on the base membrane; wherein the polyamide membrane is prepared from raw materials comprising: an amine, an inorganic salt, a silane additive, a polyacyl chloride, and an oil phase solvent; and the silane additive is at least one selected from the group consisting of 3-aminopropyltriethoxysilane, divinyltriaminopropyltrimethoxysilane, N-cyclohexyl-?-aminopropyltrimethoxysilane, and trimethoxy[3-(phenylamino)propyl]silane.

Abstract: A fabric touch device includes an upper conductor layer and a lower conductor layer. The upper conductor layer includes a first semiconductor and a first good conductor drawn out from the first semiconductor. The lower conductor layer includes a second semiconductor and a second good conductor drawn out from the second semiconductor. The upper conductor layer and the lower conductor layer remain isolated when an external force is absent. When any one of planar positions of the fabric touch device is subjected to pressure, the upper conductor layer and the lower conductor layer are in contact with each other through intersection between the first good conductor and the second good conductor, such that the first semiconductor and the second semiconductor form a conductive path, and a conduction resistance value obtained by conducting the first semiconductor and the second semiconductor uniquely corresponds to a coordinate of the planar position.

Abstract: A method for constructing a design concept generation network (DCGN) and a method for automatically generating a conceptual scheme are provided. A DCGN includes a Transformer encoder, a Transformer decoder, an importance constraint matrix generation module, an importance constraint embedding layer, a cross-attention (CA) layer, and an optimization module. A word importance constraint is ingeniously introduced based on an attention mechanism of a Transformer to record input word constraint information contained in a generated text sequence. This can effectively ensure the reliability and effectiveness of a generated conceptual scheme and is conducive to capturing potential semantic importance information and implementing semantic knowledge reasoning.

Abstract: A virtual machine (VM) hybrid graphics processing unit configuration includes a first parallel processing unit and a second parallel processing unit. The first parallel processing unit is shared among a plurality of VMs and is configured to execute operations for the plurality of VMs, wherein the operations place computational demands that are up to a threshold. The second parallel processing unit is powered up for heavier workloads when the operations for one of more of the plurality of VMs place computational demands that exceed the threshold or when selected by a user. The second parallel processing unit is assigned to execute the operations for one VM of the plurality of VMs. When the operations of the workloads issued by the VMs are under the threshold, the second parallel processing unit is powered down.

Abstract: A stacked-screen display device and a method for controlling a display device are provided. The stacked-screen display device includes a backlight module, a light control panel and a display panel which are stacked in sequence, where the backlight module includes a backplane, a reflector and a diffuser which are stacked in sequence, and the reflector is provided with a plurality of light-emitting units, the backlight module is provided with temperature sensors, the temperature sensors are configured to detect the temperature of the backlight module to compensate the display panel according to the temperature.

Abstract: An LDMOS transistor can include: an intrinsic region and a termination region distributed along, where the intrinsic region includes a semiconductor region of a first doped type, a body region of a second doped type extending from the upper surface of the semiconductor region into the interior of the semiconductor region, a drift region located in the semiconductor region, the drift region including at least one first implant region of the first doped type and at least one second implant region of the second doped type, where the at least one second implant region is separated from the body region, a source region of the first doped type located in the body region, and a drain region of the first doped type located in the semiconductor region, where the termination region includes a third implant region of the second doped type being in contact with the second implant region.

Abstract: An LDMOS transistor can include: a semiconductor region; a body region of a second doping type, wherein the body region extends from an upper surface of the semiconductor region to an interior of the semiconductor region; a source region of a first doping type and a body contact region of the second doping type, where the source region extends from an upper surface of the body region to an interior of the body region; a drain region of the first doping type, wherein the drain region is located in the semiconductor region; a source electrode that is in contact with the body contact region and the source region; and where a junction depth of the body contact region is greater than a junction depth of the source region.

Abstract: An LDMOS transistor can include: a semiconductor region; a source region of a first doping type and a drain region of the first doping type, both being disposed in the semiconductor region; a gate dielectric layer adjacent to the source region, and being disposed on an upper surface of the semiconductor region; a voltage-blocking layer adjacent to the drain region, and being disposed on the semiconductor region; a buffer field plate between the gate dielectric layer and the voltage-blocking layer, and being disposed on the upper surface of the semiconductor region; and where a thickness of the voltage-blocking layer is greater than a thickness of the buffer field plate, and the thickness of the buffer field plate is greater than a thickness of the gate dielectric layer.

Abstract: A transistor structure can include: a source region and a drain region located in a semiconductor region; a gate dielectric layer located on the upper surface of the semiconductor region; a field isolation barrier layer located on the semiconductor region, and extending laterally from the gate dielectric layer at least above the drain region and covering the upper surface of the drain region, where the field isolation barrier layer includes at least one drain via on the upper surface of the drain region; and a drain electrode filling the drain via to be in contact with the drain region.

Abstract: A follow-up swing head type large taper wire cutting device is disclosed. In the large taper wire cutting device, swing heads on upper and lower mechanical arms are adjusted in a follow-up way by swing head rotating mechanisms in coordination with a cutting taper, universal wire guide wheels are used to cooperate with the corresponding upper and lower swing heads, and tensioning mechanisms between the universal wire guide wheels and directional wire guide wheels are used for transition to ensure the smooth transition of an electrode wire, so that the electrode wire is effectively prevented from sliding off during large taper cutting, and the control of the follow-up deflection position of the electrode wire is also very accurate.

Abstract: A 6.4 Tbps silicon-based photonics engine transceiver chip module for high-speed optical communication manufactured based on processing techniques of semiconductors such as silicon-on-insulator (SOI) and indium phosphide (InP). The photonics engine transceiver chip module uses a silicon photonic chip as a substrate, and optical chips of an InP laser and an optical amplifier are heterogeneously integrated with the silicon photonic chip through bonding or flip-chip soldering. As a pump light source, the laser generates a soliton-based optical frequency comb by using an ultra-low loss silicon nitride (SiN) resonator cavity, and can be used as a multi-wavelength laser. This reduces use of a single-wavelength laser chip, reduces a power consumption and heat conduction of a laser in an optical chip of a photonic engine, and improves an integration level of an optical device. The optical frequency comb generates an optical carrier with wide bandwidth coverage and a large quantity of wavelengths.

Abstract: Disclosed is an electronic device. In embodiments of the disclosure, in a case that positions of a first feed terminal and a ground terminal are not changed, a first metal connection arm in embodiments of the disclosure has a middle section arranged with a clearance, and a length of an electric circuit of an antenna formed by a metal frame radiation section is equal to a sum of a length of a section located between a first connection position and a second connection position of the metal frame radiation section and a length of the middle section. By the middle section, a total length of the antenna is increased to a specific extent, and a length of an antenna between the first feed terminal and the ground terminal is increased.

Abstract: An electric control box includes an insulation inner shell and a fireproof outer shell. The insulation inner shell includes a first inner shell and a second inner shell that are assembled to each other. The fireproof outer shell includes a first outer shell and a second outer shell. The first outer shell covers the first inner shell, and the second outer shell covers the second inner shell. The insulation inner shell and the fireproof outer shell are parts forming a box body having a first end and a second end that are opposite to each other in a vertical direction. The second inner shell has a flow guide groove formed at an outer surface of the second inner shell and extending in the vertical direction to the first end of the box body.

Abstract: Embodiments of this application disclose an antenna system and an electronic device. The antenna system includes one NFC antenna and N conventional antennas, and each of the N conventional antennas includes a feed point, a grounding point, and a radiating branch. M conventional antennas in the N conventional antennas include blocking devices. An ith antenna includes an ith radiating branch, an ith feed point, an ith blocking device, and an ith grounding point, the ith radiating branch is coupled to the ith feed point, and the ith radiating branch is coupled to the ith grounding point through the ith blocking device. The blocking device is configured to block a radio frequency signal in a frequency band of the NFC antenna in the M conventional antennas. The M conventional antennas are within a field strength range of radiation of the NFC antenna. Radiation performance of the NFC antenna is improved.

Abstract: A control method includes obtaining an operating instruction including a set operating duration, determining a first maximum operating power of an air conditioner of a vehicle according to the set operating duration and a current remaining charge of a battery of the vehicle, controlling the air conditioner to operate in a power range not exceeding the first maximum operating power, recording a continuous operating duration of the air conditioner and obtaining a real-time remaining charge of the battery, determining a second maximum operating power of the air conditioner according to the continuous operating duration and the real-time remaining charge, and controlling the air conditioner to continue operating in a power range not exceeding the second maximum operating power.

Abstract: An anti-eavesdropping distributed fusion filtering method for the multi-rate nonlinear system over sensor network includes: Step 1, establishing a dynamic model for the multi-rate nonlinear system over sensor network; Step 2, transforming the multi-rate nonlinear system dynamic model into a single-rate nonlinear system dynamic model through the prediction compensation strategy; Step 3, designing an anti-eavesdropping distributed fusion filter; Step 4, calculating an upper bound on the one-step prediction error covariance (tk+1|tk); Step 5, deriving the local distributed filter parameter Ki(tk+1); Step 6, deriving the selection matrix Lij(tk+1); Step 7, substituting Ki(tk+1) and Lij(tk+1) into Step 3 to obtain the fusion filter {circumflex over (x)}CI(tk+1|+tk+1); Step 8, solving for the upper bound on the local filtering error covariance (tk+1|tk+1).

Abstract: A window air conditioner includes a base, and a casing assembly mounted at the base and including an inner casing and an outer casing spaced apart from each other. The outer casing includes an outdoor heat exchanger at a side of the outer casing facing away from the inner casing. The window air conditioner further includes an electric control box disposed in the outer casing. The electric control box includes a box body and a radiator at least partially provided in the box body. The radiator includes a bottom plate located in the box body and approximately parallel to the outdoor heat exchanger.

Abstract: The present invention relates to a post-exascale graph computing method, and corresponding system, storage medium and electronic device. The invention solves the problems of low computing performance, poor scalability and high communication overhead in the large-scale distributed environment, and improves the performance of the supercomputer when supporting large-scale graph computing.