Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

Abstract: A noise reduction device for audio equipment includes a microprocessor, a digital signal processor, a host computer interface and an audio terminal. The digital signal processor is electrically connected to the microprocessor. The digital signal processor includes an uplink signal processing module and a downlink signal processing module. The host computer interface is configured to connect to a host computer. The host computer interface is electrically connected to the microprocessor. The audio connection terminal is configured to connect to the audio equipment. The audio connection terminal is electrically connected to the microprocessor. The uplink signal processing module is configured to perform noise reduction processing on an uplink signal of the audio equipment. The downlink signal processing module is configured to perform noise reduction processing on a downlink signal of the host computer.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A speaker is provided and includes a first speaker body, a second speaker body, a speaker component, and a sound transmission member. The first speaker body has a first chamber. The second speaker body has a second chamber. The second speaker body is received in the first chamber and defines a resonant cavity in the first chamber. The speaker component is disposed on the second speaker body and includes a supporting member, a magnet, a coil, and a diaphragm. Two ends of the supporting member are respectively inserted into the second chamber and fixed on the second speaker body. The magnet is disposed in the supporting member. The diaphragm is disposed on the supporting member and abuts against the second speaker body. The coil is received in the magnet and is connected to the diaphragm. The sound transmission member is coaxially disposed in the resonant cavity with the speaker component.

Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.

Abstract: An IC device includes a heat spreader, an electronic component over the heat spreader, an optical component over the electronic component, a multilayer structure over the optical component, and a redistribution structure over the multilayer structure. The multilayer structure includes a waveguide optically coupled to the optical component. The redistribution structure is electrically coupled to the electronic component by vias through the optical component and the multilayer structure.

Abstract: A method includes tagging source PDK devices (SPDs) in a source-circuit design (SCD); generating a source design simulation database (SDSD) based on source design key performance indicator (KPI) simulation data of the SPDs in the SCD; generating a target process design kit (PDK) simulation database (TPSD) based on target design KPI simulation data of a plurality of target-PDK devices (TPDs); creating a matching table based on the SDSD and the TPSD; matching, based on the matching table, one or more TPDs from the TPSD with each SPD in the SDSD based on SPD KPIs; ranking the one or more TPDs matched from the TPSD with each SPD in the SDSD based on the SPD KPIs; and exchanging, based on a migration mapping table that includes a one-to-one relationship for TPDs to the SPDs in the SCD, one or more SPDs in the SCD with one-to-one relational TPDs.

Abstract: An image processing method including the following steps is provided. An image information of an image is received, wherein the image includes a plurality of blocks and the image information includes a plurality of pixel information of each block. A dual gamma correction is performed on a first group of blocks of the image to obtain one or more corrected blocks and the dual gamma correction is skipped on a second group of blocks of the image to obtain a plurality of uncorrected blocks. A first encoding process is performed on the one or more corrected blocks to obtain a plurality of first encoded blocks. A second encoding process different from the first encoding process is performed on the plurality of uncorrected blocks to obtain a plurality of second encoded blocks.

Abstract: Circuits and methods for adding a Current Mode signal into a Voltage Mode controller for fixed-frequency DC-to-DC power converters. A current-controlled voltage source (CCVS) generates a voltage proportional to the power converter output current, which voltage is combined with a comparison signal generated by comparing a target output voltage to the actual output voltage. The modified comparison signal generates a pulse-width modulation control signal that regulates the power converter output as a function of output voltage and some portion of output current. With the addition of an inductor current signal into the controller Voltage Mode feedback loop, the double pole predominant in constant conduction mode (CCM) mode can be smoothed over to improve stability, while discontinuous conduction mode (DCM) loop response is largely unchanged with or without the added Current Mode signal. Embodiments enable simplified compensation while covering a wider operating range.

Abstract: A test key structure includes a substrate; a first metal pad disposed on the substrate; a second metal pad disposed in proximity to the first metal pad on the substrate; a gap between the first metal pad and the second metal pad; a first contact disposed on the first metal pad; and a second contact disposed on the second metal pad.

Abstract: A stacked-screen display device and a method for controlling a display device are provided. The stacked-screen display device includes a backlight module, a light control panel and a display panel which are stacked in sequence, where the backlight module includes a backplane, a reflector and a diffuser which are stacked in sequence, and the reflector is provided with a plurality of light-emitting units, the backlight module is provided with temperature sensors, the temperature sensors are configured to detect the temperature of the backlight module to compensate the display panel according to the temperature.

Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.

Abstract: An integrated circuit (IC) for controlling a power converter. The IC includes a controller that, in a first sensing period, enables a sensing circuit of the power converter and electrically connects an output node of an op amp of the sensing circuit and a first node of a capacitor of the sensing circuit, creating a first voltage across the capacitor; in a period between the first sensing period and a second sensing period, disables the sensing circuit and disconnects the output node of the op amp and the first node of the capacitor to maintain the first voltage across the capacitor; and in the second sensing period, enables the sensing circuit and connects the output node of the op amp and the first node of the capacitor, the maintained first voltage across the capacitor reducing a settling time for the enabled sensing circuit.

Abstract: Provided is a package including: a die having an upper surface and including at least one conductive pad disposed adjacent to the upper surface; a first pillar structure over the die; and a second pillar structure aside the first pillar structure, wherein the second pillar structure is electrically connected to the conductive pad of the die, and defining a recess portion recessed from a side surface of the second pillar structure, wherein the second pillar structure and the conductive pad have different conductivities.

Abstract: A semiconductor structure includes, an optical component and a thermal control mechanism. The optical component includes a first main path that splits into a first side path and a second side path so that the first side path and the second side path are separated from one another. The thermal control mechanism configured to control a temperature of both the first side path and the second side path, wherein the first thermal control mechanism includes a first thermoelectric member and a second thermoelectric member that are positioned between the first side path and the second side path and the first thermoelectric member and the second thermoelectric member have opposite conductive types.

Abstract: Methods and devices for sensing current through a power converter circuit are presented. According to one aspect, currents through high-/low-side transistors are sensed via respective reduced size replica transistors. According to another aspect, the sensed currents are used to generate bridging currents that are combined with the sensed currents to generate a continuous current sense signal. According to another aspect, the bridging currents include slopes that are generated from slopes of the sensed currents. According to another aspect, the sensed currents are combined and filtered to generate a continuous sense signal. According to another aspect, the continuous current sense signal is a voltage that is compared to a reference voltage to generate a current limit status flag used to control operation of the power converter circuit. According to other aspects, the current sense voltage is used to control ON/OFF duty cycle of the power converter circuit.

Abstract: The present disclosure provides a flight anti-collision method and apparatus based on electromagnetic field detection of an overhead transmission line. An example method includes: determining whether an overhead transmission line around is an Alternating Current (AC) transmission line or a (Direct Current) DC transmission line; if the overhead transmission line is an AC transmission line, determining a position relationship between an aircraft and the overhead transmission line on the basis of a phase distribution model and an electric field phase and a magnetic field phase measured by a phase detector on the aircraft; if the overhead transmission line around is a DC transmission line, determining the position relationship between the aircraft and the overhead transmission line on the basis of a magnetic field intensity distribution model and the magnetic field intensities collected by magnetic field intensity sensors on the aircraft; and thus controlling the aircraft.

Abstract: A conjugate comprising a cyclic peptide scaffold and one or more N-acetylgalactosamine (GalNAc) moieties. The conjugate may further carry a diagnostic or therapeutic agent for use in delivering the agent to liver cells. In some embodiments, the cyclic peptide may have 4-10 amino acid residues. The GalNAc moieties can be covalently bound to the cyclic peptide scaffold via a first linker and the agent can be covalently bound to the cyclic peptide scaffold via a second linker.