Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A double-sided flexible circuit board includes a flexible substrate, a first circuit layer, a second circuit layer, an insulating protection layer and a plurality of through circuit lines. The first and second circuit layers are located on a top surface and a bottom surface of the flexible substrate, respectively. The insulating protection layer covers a supporting line of the second circuit layer such that the supporting line is located between the flexible substrate and the insulating protection layer. The insulating protection layer can provide electrical insulation to the supporting line of the second circuit layer to avoid short circuit conditions of the double-sided flexible circuit board during test.

Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.

Abstract: Disclosed in embodiments of the present disclosure are a communication terminal, a communication system and an audio information processing method, the communication terminal includes a sound reception assembly and a basic communication module, wherein the basic communication module of the communication terminal receives second pickup audio information in a wireless manner, such that the communication terminal acquires returned audio information according to first pickup audio information generated by the communication terminal and the received second pickup audio information, and transmits outwards the returned audio information. Therefore, the technical solution in the embodiments of the present disclosure may realize synchronous sound reception of a plurality of wireless sound reception apparatuses or wireless sound reception components, and may satisfy a requirement for multiple people to use, thereby achieving a good sound reception effect.

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

Abstract: A sensing device includes a sensing circuit, a conductive line, and a sampling circuit. The conductive line is electrically connected to the sensing circuit. The sampling circuit is electrically connected to the conductive line. The sampling circuit includes a capacitor, a first thin film transistor, and a second thin film transistor. The first terminal of the first thin film transistor is electrically connected to the first terminal of the capacitor. The first terminal of the second thin film transistor is electrically connected to the second terminal of the capacitor. The second terminal of the first thin film transistor is electrically connected to the conductive line. The second terminal of the second thin film transistor is electrically connected to the ground terminal.

Abstract: An electronic device has a photosensitive element, a charge storage element, and a node. The photosensitive element generates a current in response to illumination thereon. The charge storage element is coupled to the photosensitive element and is used to store charge in response to the current generated by the photosensitive element. The signal reading circuit is coupled to the photosensitive element, and the node is coupled between the photosensitive element and the charge storage element. The charge storage element and the photosensitive element are coupled in series, and the node is coupled to an end of the signal reading circuit.

Abstract: A sensing device, including a plurality of sensing pixels arranged in Y rows and M columns, a plurality of readout lines coupled to the sensing pixels, and a plurality of control lines each coupled to a sensing pixel subset, is provided. The Y times N sensing pixels within the sensing pixel subset are arranged in adjacent N columns, where Y, M and N are integers and N is smaller than M. Each of the control lines is configured to control one row of the sensing pixel subset to output signals through corresponding readout lines.

Abstract: A semiconductor package structure includes a semiconductor package structure includes a first supporting bar, a second supporting bar and an encapsulant. The second supporting bar is adjacent to the first supporting bar. The first supporting bar and the second supporting bar extend substantially along a first direction. The encapsulant covers the first supporting bar and the second supporting bar. The encapsulant defines a first recess and a second recess recessed from a lower surface of the encapsulant. The first recess extends substantially along a second direction different from the first direction. The second recess is located between the first recess and the second supporting bar.

Abstract: An electronic device includes a photodiode, a first transistor, a second transistor, a third transistor and a capacitor. The photodiode has a first terminal and a second terminal. The first transistor has a control terminal used to receive a reset signal, a first terminal coupled to the second terminal of the photodiode, and a second terminal. The second transistor has a control terminal coupled to the second terminal of the photodiode, a first terminal and a second terminal. The third transistor has a control terminal used to receive a row selection signal, a first terminal coupled to the second terminal of the second transistor, and a second terminal. The capacitor has a first terminal coupled to the second terminal of the photodiode, and a second terminal coupled to the second terminal of the first transistor.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: A semiconductor package structure includes a semiconductor package structure includes a first supporting bar, a second supporting bar and an encapsulant. The second supporting bar is adjacent to the first supporting bar. The first supporting bar and the second supporting bar extend substantially along a first direction. The encapsulant covers the first supporting bar and the second supporting bar. The encapsulant defines a first recess and a second recess recessed from a lower surface of the encapsulant. The first recess extends substantially along a second direction different from the first direction. The second recess is located between the first recess and the second supporting bar.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.