Patents by Inventor Hui-Yu Lee
Hui-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250130379Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.Type: ApplicationFiled: November 26, 2024Publication date: April 24, 2025Inventors: Yu-Hao CHEN, Hui-Yu LEE, Chung-Ming WENG, Jui-Feng KUAN, Chien-Te WU
-
Patent number: 12271029Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: GrantFiled: May 24, 2024Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
-
Publication number: 20250093765Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.Type: ApplicationFiled: December 5, 2024Publication date: March 20, 2025Inventors: YU-HAO CHEN, HUI-YU LEE, JUI-FENG KUAN, CHIEN-TE WU
-
Patent number: 12197123Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.Type: GrantFiled: October 20, 2023Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hao Chen, Hui-Yu Lee, Jui-Feng Kuan, Chien-Te Wu
-
Patent number: 12181722Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.Type: GrantFiled: August 9, 2023Date of Patent: December 31, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Hui-Yu Lee, Chung-Ming Weng, Jui-Feng Kuan, Chien-Te Wu
-
Publication number: 20240413052Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.Type: ApplicationFiled: July 31, 2024Publication date: December 12, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsiang HUANG, Chin-Chou LIU, Chin-Her CHIEN, Fong-yuan CHANG, Hui Yu LEE
-
Patent number: 12167509Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.Type: GrantFiled: December 27, 2022Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hui Yu Lee
-
Patent number: 12154842Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.Type: GrantFiled: July 5, 2023Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
-
Publication number: 20240361546Abstract: In a method, a stacked structure including an electronic integrated circuit (IC) and a photonic IC is bonded to a heat spreader releasably attached to a carrier. A first multilayer structure is sequentially deposited and patterned over the stacked structure to form, in the first multilayer structure, a first waveguide optically coupled to the photonic IC. A redistribution structure is sequentially deposited and patterned over the first multilayer structure, the redistribution structure electrically coupled to the photonic IC. The carrier is detached from the heat spreader.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Inventors: Yu-Hao CHEN, Hui Yu LEE
-
Publication number: 20240355769Abstract: A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei Kuo, Hui-Yu Lee
-
Publication number: 20240345425Abstract: A method includes forming, over a substrate, an optical component and first, second and third thermal control mechanisms. The optical component includes first and second main paths, and first and second side paths each having opposite ends correspondingly coupled to the first and second main paths. The second side path is spaced from the first side path. Each of the first, second and third thermal control mechanisms includes a first thermoelectric member having a first conductivity type, a second thermoelectric member having a second conductivity type opposite to the first conductivity type, and a conductive structure that electrically connects the first thermoelectric member to the second thermoelectric member. The first side path is between the first and third thermal control mechanisms. The second side path is between the second and third thermal control mechanisms. The third thermal control mechanism is between the first and second side paths.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Inventors: Yu-Hao CHEN, Hui Yu LEE, Jui-Feng KUAN, Chien-Te WU
-
Publication number: 20240310576Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: ApplicationFiled: May 24, 2024Publication date: September 19, 2024Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
-
Patent number: 12085769Abstract: An IC device includes a heat spreader, an electronic component over the heat spreader, an optical component over the electronic component, a multilayer structure over the optical component, and a redistribution structure over the multilayer structure. The multilayer structure includes a waveguide optically coupled to the optical component. The redistribution structure is electrically coupled to the electronic component by vias through the optical component and the multilayer structure.Type: GrantFiled: July 2, 2021Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee
-
Publication number: 20240296268Abstract: A method includes tagging source PDK devices (SPDs) in a source-circuit design (SCD); generating a source design simulation database (SDSD) based on source design key performance indicator (KPI) simulation data of the SPDs in the SCD; generating a target process design kit (PDK) simulation database (TPSD) based on target design KPI simulation data of a plurality of target-PDK devices (TPDs); creating a matching table based on the SDSD and the TPSD; matching, based on the matching table, one or more TPDs from the TPSD with each SPD in the SDSD based on SPD KPIs; ranking the one or more TPDs matched from the TPSD with each SPD in the SDSD based on the SPD KPIs; and exchanging, based on a migration mapping table that includes a one-to-one relationship for TPDs to the SPDs in the SCD, one or more SPDs in the SCD with one-to-one relational TPDs.Type: ApplicationFiled: June 19, 2023Publication date: September 5, 2024Inventors: Fong-Yuan CHANG, Hui Yu LEE, Yu-Hao CHEN, Tian-Jian WU, Tien-Chien HUANG, Manjo Kumar ENUGULA, Yu-Lin WEI, Jyun-Hao CHANG
-
Patent number: 12068269Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.Type: GrantFiled: April 25, 2023Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei Kuo, Hui-Yu Lee
-
Patent number: 12062641Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.Type: GrantFiled: May 23, 2023Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Hui-Yu Lee, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
-
Patent number: 12055800Abstract: A semiconductor structure includes, an optical component and a thermal control mechanism. The optical component includes a first main path that splits into a first side path and a second side path so that the first side path and the second side path are separated from one another. The thermal control mechanism configured to control a temperature of both the first side path and the second side path, wherein the first thermal control mechanism includes a first thermoelectric member and a second thermoelectric member that are positioned between the first side path and the second side path and the first thermoelectric member and the second thermoelectric member have opposite conductive types.Type: GrantFiled: July 27, 2021Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
-
Patent number: 12029123Abstract: A semiconductor structure includes an optical component and a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component. The thermal control mechanism includes a conductive structure, a first thermoelectric member and a second thermoelectric member opposite to the first thermoelectric member. The first thermoelectric member and the second thermoelectric member are electrically connected to the conductive structure. The first thermoelectric member and the second thermoelectric member have opposite conductive types. The semiconductor structure further includes a first dielectric layer surrounding the optical component and a portion of the thermal control mechanism, wherein the conductive structure is over the first dielectric layer, and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer.Type: GrantFiled: April 22, 2021Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan
-
Patent number: 11994713Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: GrantFiled: March 20, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
-
Publication number: 20240045322Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: YU-HAO CHEN, HUI-YU LEE, JUI-FENG KUAN, CHIEN-TE WU