Patents by Inventor Hui-Yu Lee

Hui-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535635
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
  • Publication number: 20200006325
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Publication number: 20200006194
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Application
    Filed: June 6, 2019
    Publication date: January 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hsiang HUANG, Chin-Chou LIU, Chin-Her CHIEN, Fong-yuan CHANG, Hui Yu LEE
  • Publication number: 20190385980
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Chih-Lin CHEN, Chin-Chou LIU, Fong-Yuan CHANG, Hui-Yu LEE, Po-Hsiang HUANG
  • Patent number: 10475890
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu, Scott Beasor, Erik Geiss, Jerome Ciavatti, Jae Gon Lee
  • Patent number: 10467375
    Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Hao-Tien Kan
  • Publication number: 20190280105
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Patent number: 10383528
    Abstract: A wearable apparatus and a photoplethysmograph (PPG) sensor unit are provided. The wearable apparatus includes a wearable holder and a physiological information measurement module configured to the wearable holder. The physiological information measurement module includes a circuit board, an electrocardiograph (ECG) sensor unit and a PPG sensor unit. The PPG sensor unit is disposed on the circuit board and adapted to be used in conjunction with the ECG sensor unit electrically connected to a first pad and a second pad on the circuit board. The PPG sensor unit includes a grid having a plurality of accommodating spaces, a lighting element arranged in one of the accommodating spaces, and a photo sensor arranged in another accommodating space. The grid includes an inner conductive contact portion exposed from the wearable holder, facing an inner side of the wearable holder and electrically connected to the second pad.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 20, 2019
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Tsan-Yu Ho, Meng-Sung Chou, Ming-Kun Weng, Chiou-Yueh Wang, Fang-Yi Chang, Ren-Guey Lee, Hui-Chia Kuo
  • Patent number: 10365486
    Abstract: A head up display (HUD) includes a housing having an opening, a transmission mechanism disposed in the housing, a cover connected to the transmission mechanism and a drive mechanism configured to drive the transmission mechanism. The cover is movable between a closed position wherein the cover hides the opening and an opened position wherein the cover is located within the housing by the transmission mechanism. While the cover moves from the closed position to the opened position, the cover moves to an intermediate position below the opening in a vertical way, and moves away from the intermediate position below the opening to the opened position in sequence.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: July 30, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Wei Huang, Chun-Yu Lee, Hui-Ching Tsai
  • Publication number: 20190129272
    Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 2, 2019
    Inventors: Hui-Yu LEE, Jui-Feng KUAN
  • Patent number: 10268788
    Abstract: A method includes building a driver model in frequency domain, extracting S (scattering) parameters, the S parameters to describe a real curve that represents a real signal channel between the driver model and a load circuit, and generating, based on the extracted S parameters, an approaching curve of the real curve, the approaching curve being expressed in an approaching equation.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hui-Yu Lee, Hao-Tien Kan
  • Publication number: 20190069347
    Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventor: HUI YU LEE
  • Publication number: 20190034578
    Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.
    Type: Application
    Filed: October 2, 2018
    Publication date: January 31, 2019
    Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
  • Patent number: 10192833
    Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
  • Publication number: 20180373113
    Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 27, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Yu LEE, Jui-Feng KUAN
  • Patent number: 10163787
    Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10162244
    Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Yu Lee, Jui-Feng Kuan
  • Patent number: 10157252
    Abstract: An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first inter layer via (ILV) to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for engineering change order (ECO) purpose.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Publication number: 20180336305
    Abstract: A method includes building a driver model in frequency domain, extracting S (scattering) parameters, the S parameters to describe a real curve that represents a real signal channel between the driver model and a load circuit, and generating, based on the extracted S parameters, an approaching curve of the real curve, the approaching curve being expressed in an approaching equation.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Inventors: HUI-YU LEE, HAO-TIEN KAN
  • Patent number: 10095827
    Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng