Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.

Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.

Abstract: A method includes building a driver model in frequency domain, extracting S (scattering) parameters, the S parameters to describe a real curve that represents a real signal channel between the driver model and a load circuit, and generating, based on the extracted S parameters, an approaching curve of the real curve, the approaching curve being expressed in an approaching equation.

Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.

Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.

Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.

Abstract: A device is disclosed that includes a comparator and a configurable heater. The comparator is configured to compare a transmission phase of a light transmitted in a photonic component with a reference phase to generate a phase difference. The configurable heater is disposed with respect to the photonic component and includes a plurality of heater segments, wherein a number of the heater segments in operation is trimmable based on the phase difference.

Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.

Abstract: An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first inter layer via (ILV) to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for engineering change order (ECO) purpose.

Abstract: A method includes building a driver model in frequency domain, extracting S (scattering) parameters, the S parameters to describe a real curve that represents a real signal channel between the driver model and a load circuit, and generating, based on the extracted S parameters, an approaching curve of the real curve, the approaching curve being expressed in an approaching equation.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.

Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.

Abstract: A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.

Abstract: A method includes generating a schematic of an integrated circuit (IC), the IC having a circuit component. The method also includes searching a database having one or more configurations of the circuit component, each of the one or more configurations of the circuit component having a corresponding estimated resistance capacitance (RC) value and an assigned color scheme based on the estimated RC value. The method further includes displaying the circuit component in the schematic as a symbol representing the circuit component, the symbol representing the circuit component being displayed having the assigned color scheme of a selected circuit component configuration.