Patents by Inventor Hui-Yu Lee
Hui-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11043473Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: GrantFiled: December 18, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
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Publication number: 20210159225Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
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Patent number: 10971485Abstract: An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.Type: GrantFiled: February 22, 2019Date of Patent: April 6, 2021Inventors: Hui Yu Lee, Ka Fai Chang
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Patent number: 10943729Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.Type: GrantFiled: June 28, 2019Date of Patent: March 9, 2021Inventors: Ka Fai Chang, Chin-Chou Liu, Fong-Yuan Chang, Hui Yu Lee, Yi-Kan Cheng
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Publication number: 20210057365Abstract: A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.Type: ApplicationFiled: February 26, 2020Publication date: February 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Wei Kuo, Hui-Yu Lee
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Patent number: 10910365Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.Type: GrantFiled: September 12, 2019Date of Patent: February 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
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Patent number: 10763253Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.Type: GrantFiled: August 28, 2017Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20200258846Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Chin-Chou LIU, Cheng-Hung YEH, Fong-Yuan CHANG, Po-Hsiang HUANG, Yi-Kan CHENG, Ka Fai CHANG
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Publication number: 20200252999Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.Type: ApplicationFiled: March 30, 2020Publication date: August 6, 2020Inventor: HUI YU LEE
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Publication number: 20200168527Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.Type: ApplicationFiled: September 6, 2019Publication date: May 28, 2020Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheny-hung YEH, Hui Yu LEE, Po-Hsiang HUANG, Yi-Kan CHENG
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Patent number: 10665550Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: GrantFiled: July 24, 2018Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Publication number: 20200151382Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
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Publication number: 20200135388Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.Type: ApplicationFiled: June 28, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ka Fai CHANG, Chin-Chou LIU, Fong-Yuan CHANG, Hui Yu LEE, Yi-Kan CHENG
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Publication number: 20200135709Abstract: An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.Type: ApplicationFiled: February 22, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Ka Fai CHANG
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Patent number: 10638543Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.Type: GrantFiled: August 31, 2017Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hui Yu Lee
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Patent number: 10634972Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.Type: GrantFiled: December 17, 2018Date of Patent: April 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hui-Yu Lee, Jui-Feng Kuan
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Publication number: 20200126952Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Chih-Lin CHEN, Chin-Chou LIU, Fong-Yuan CHANG, Hui-Yu LEE, Po-Hsiang HUANG
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Patent number: 10540475Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.Type: GrantFiled: October 2, 2018Date of Patent: January 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20200020644Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: ApplicationFiled: July 24, 2018Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Patent number: 10535635Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: GrantFiled: June 15, 2018Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang