Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced parasitic capacitance between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including first and second fins; an isolation structure between the fins; first and second metal gates; a first dielectric body under the first metal gate and on the substrate between the first fin and the second fin, wherein a top of the first dielectric body is below a top of the first metal gate; and a second dielectric body in the second metal gate and on the substrate between the first fin and the second fin, wherein a top of the second dielectric body is at or above a top of the second metal gate.

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.

Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.

Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.

Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an ?-Si layer in a recess over the epi S/D; forming an oxide layer over the ?-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and ?-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.

Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods.