Abstract: A method for forming a semiconductor structure includes alternately forming a plurality of channel layers and a plurality of sacrificial layers over a substrate. The method also includes forming a source/drain trench through the channel layers and the sacrificial layers. The method also includes replacing the sacrificial layers with a plurality of dummy oxide layers. Sidewalls of the dummy oxide layers are substantially aligned with sidewalls of the channel layers. The method also includes selectively forming a plurality of inner spacers on the sidewalls of the dummy oxide layers through the source/drain trench. The method also includes replacing the dummy oxide layers with a gate structure.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region in which sacrificial layers and channel layers are alternately stacked. A topmost one of the channel layers is a first channel layer. The method further includes forming a first source/drain feature on the first active region, removing the sacrificial layers of the first active region to form first gaps, at least partially removing the first channel layer of the first active region, and forming a first gate stack to fill the first gaps.

Abstract: A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further includes forming a hard mask on the shallow trench isolation region, forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, forming a disposable interposer in the space, removing the dummy gate stack, removing the disposable interposer using an etching chemical, wherein when the disposable interposer is removed, the hard mask is exposed to the etching chemical, and forming a gate stack, wherein a portion of the gate stack is filled in the space.

Abstract: A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further includes forming a hard mask on the shallow trench isolation region, forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, forming a disposable interposer in the space, removing the dummy gate stack, removing the disposable interposer using an etching chemical, wherein when the disposable interposer is removed, the hard mask is exposed to the etching chemical, and forming a gate stack, wherein a portion of the gate stack is filled in the space.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a fin-shape base protruding from a semiconductor substrate. A top surface of the semiconductor substrate is in a (100) crystal plane, and a top surface of the fin-shape base is in a (110) crystal plane. The semiconductor device also includes channel members disposed over the top surface of the fin-shape base, a gate structure wrapping around at least one of channel members, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the channel members, and a dopant-free epitaxial feature under the source/drain feature. A top surface of the source/drain feature is in a (110) crystal plane. A top surface of the dopant-free epitaxial feature is in a (110) crystal plane.

Abstract: An integrated circuit includes an interlevel dielectric layer having a first portion directly above a source/drain region of a transistor and a second portion directly above the source/drain region and laterally abutting the first portion. The first and second portions have different material compositions such that that the interlevel dielectric region imparts a beneficial strain to the transistor.

Abstract: A semiconductor device includes an isolation structure over a substrate, a fin-shaped base protruding from the substrate and through the isolation structure, channel members vertically stacked above the fin-shaped base, first and second dielectric fins over the isolation structure and sandwiching the channel members, an epitaxial feature atop the fin-shaped base and abutting the channel members, a gate structure wrapping around at least one of the channel members, and a gate spacer extending along a sidewall of the gate structure. Bottom surfaces of the first and second dielectric fins are above a top surface of the isolation structure. An interface between the epitaxial feature and the fin-shaped base is above the top surface of the isolation structure.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.

Abstract: A semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers. A portion of the epitaxial S/D feature is horizontally surrounded by the oxide layer.

Abstract: Methods and structures for inserting disposable interposers include forming a first gate over a first fin and a first spacer layer on sidewalls of the first gate, and a second gate over a second fin and a second spacer layer on sidewalls of the second gate. The method further includes replacing, within the first fin, epitaxial layers of a second composition with disposable interposers disposed beneath the first gate and first inner spacers on opposing ends of the disposable interposers. The method further includes etching back, within the second fin, opposing lateral ends of the epitaxial layers of the second composition to form recesses disposed beneath the second spacer layer and between adjacent epitaxial layers of the first composition. The method further includes forming second inner spacers, within the second fin, within each of the recesses on the opposing lateral ends of the epitaxial layers of the second composition.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include bonding a first semiconductor substrate having (110) orientation on a second semiconductor substate having (100) orientation, forming a stack over the first semiconductor substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning the stack to form a fin-shape structure, the fin-shape structure comprising a channel region and a source/drain region, recessing the source/drain region to form a source/drain trench, forming a dielectric film in the source/drain trench, and epitaxially growing an epitaxial feature over the dielectric film, the epitaxial feature being in contact with the plurality of channel layers. The epitaxial feature has (110) orientation.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant contains halide. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

Abstract: Semiconductor structures and methods are provided. In an embodiment, a semiconductor structure includes a substrate including a first mesa structure and a second mesa structure, an isolation feature extending between the first mesa structure and the second mesa structure, a first vertical stack of nanostructures directly over the first mesa structure, first source/drain features coupled to the first vertical stack of nanostructures, a dielectric layer comprising a first portion disposed on the isolation feature and a second portion disposed between the first-type source/drain features and the substrate, and a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures.

Abstract: A semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers. A portion of the epitaxial S/D feature is horizontally surrounded by the oxide layer.

Abstract: A method includes forming a structure having a dummy gate stack over a multi-layer stack (ML) disposed on a semiconductor substrate, the ML including alternating channel layers and non-channel layers; recessing the ML in source/drain (S/D) regions; removing the non-channel layers to form first openings between the channel layers; depositing a dielectric material in the first openings; recessing the dielectric material to form undercuts; forming inner spacers in the undercuts; forming epitaxial S/D features in the S/D regions; removing the dummy gate stack to form a gate trench; removing the dielectric material from the gate trench to form second openings between the channel layers; and forming a metal gate stack in the gate trench and the second openings.

Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.