Patents by Inventor Huiling Shang
Huiling Shang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7790538Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: May 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
-
Patent number: 7682968Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: April 23, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
-
Publication number: 20090212366Abstract: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.Type: ApplicationFiled: May 1, 2009Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Wilfried E. Haensch, Meikei Ieong, Ghavam Shahidi, Huiling Shang
-
Patent number: 7521376Abstract: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.Type: GrantFiled: October 26, 2005Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Martin M. Frank, Steven J. Koester, John A. Ott, Huiling Shang
-
Patent number: 7449782Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: May 4, 2004Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
-
Publication number: 20080248616Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: May 10, 2008Publication date: October 9, 2008Applicant: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
-
Publication number: 20080227283Abstract: A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: ApplicationFiled: April 23, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
-
Publication number: 20080220606Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: ApplicationFiled: April 23, 2008Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
-
Patent number: 7387925Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: April 10, 2007Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
-
Publication number: 20070287256Abstract: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.Type: ApplicationFiled: June 7, 2006Publication date: December 13, 2007Applicant: International Business Machines CorporationInventors: Leland Chang, Wilfried E. Haensch, Meikei Ieong, Ghavam Shahidi, Huiling Shang
-
Publication number: 20070218621Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: April 10, 2007Publication date: September 20, 2007Applicant: International Business Machines CorporationInventors: Huiling Shang, Meikei Leong, Jack Chu, Kathryn Guarini
-
Patent number: 7244958Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: June 24, 2004Date of Patent: July 17, 2007Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
-
Publication number: 20070093074Abstract: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.Type: ApplicationFiled: October 26, 2005Publication date: April 26, 2007Applicant: International Business Machines CorporationInventors: Martin Frank, Steven Koester, John Ott, Huiling Shang
-
Publication number: 20060202279Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.Type: ApplicationFiled: April 29, 2006Publication date: September 14, 2006Applicant: International Business Machines CorporationInventors: Evgeni Gousev, Huiling Shang, Christopher D'Emic, Paul Kozlowski
-
Patent number: 7078300Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.Type: GrantFiled: September 27, 2003Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Evgeni Gousev, Huiling Shang, Christopher P. D'Emic, Paul M. Kozlowski
-
Publication number: 20050285097Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Inventors: Huiling Shang, Meikei Ieong, Jack Chu, Kathryn Guarini
-
Publication number: 20050250301Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: ApplicationFiled: May 4, 2004Publication date: November 10, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
-
Publication number: 20050082624Abstract: A structure, and method of fabrication, for high performance semiconductor field effect devices is disclosed. These devices are having a gate dielectric containing a germanate material. In representative embodiments the gate dielectric is essentially a layer of a germanate material. The chemical composition of such materials is MezGexOy, where Me stands for a metal with high ion polarizability, and x, y, and z are non-zero integers. Such a gate dielectric is advantageous, from the point of view of dielectric constant, barrier height, carrier mobility, thermal stability, and interface stability.Type: ApplicationFiled: October 20, 2003Publication date: April 21, 2005Inventors: Evgeni Gousev, Alessandro Callegari, Dianne Lacey, Deborah Neumayer, Huiling Shang
-
Publication number: 20050070122Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.Type: ApplicationFiled: September 27, 2003Publication date: March 31, 2005Inventors: Evgeni Gousev, Huiling Shang, Christopher D'Emic, Paul Kozlowski
-
Patent number: 6803266Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.Type: GrantFiled: March 20, 2003Date of Patent: October 12, 2004Assignee: International Business Machines CorporationInventors: Paul M. Solomon, Douglas A. Buchanan, Eduard A. Cartier, Kathryn W. Guarini, Fenton R. McFeely, Huiling Shang, John J. Yourkas