Patents by Inventor Huiling Shang
Huiling Shang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8969969Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.Type: GrantFiled: March 19, 2010Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan, Roger Allen Booth, Jr.
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Publication number: 20150021625Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.Type: ApplicationFiled: October 9, 2014Publication date: January 22, 2015Inventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang, Reinaldo A. Vega
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Patent number: 8933528Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.Type: GrantFiled: March 11, 2013Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang, Reinaldo A. Vega
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Patent number: 8928086Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.Type: GrantFiled: January 9, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Dechao Guo, Myung-Hee Na, Ravikumar Ramachandran, Kern Rim, Huiling Shang
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Patent number: 8927361Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.Type: GrantFiled: March 13, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Roger Allen Booth, Jr., Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan
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Publication number: 20140377924Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.Type: ApplicationFiled: September 9, 2014Publication date: December 25, 2014Inventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Dechao Guo, Myung-Hee Na, Ravikumar Ramachandran, Kern Rim, Huiling Shang
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Publication number: 20140252413Abstract: A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Myung-Hee Na, Ravikumar Ramachandran, Huiling Shang
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Publication number: 20140252479Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang, Reinaldo A. Vega
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Publication number: 20140191297Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Inventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Dechao Guo, Myung-Hee Na, Ravikumar Ramachandran, Kern Rim, Huiling Shang
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Patent number: 8685818Abstract: Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.Type: GrantFiled: June 25, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Huiling Shang, Ying Li, Henry K. Utomo
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Patent number: 8592264Abstract: A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.Type: GrantFiled: December 21, 2011Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Takashi Ando, Huiming Bu, Ramachandra Divakaruni, Bruce B. Doris, Chung-Hsun Lin, Huiling Shang, Tenko Yamashita
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Patent number: 8558313Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: GrantFiled: March 21, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Publication number: 20130161763Abstract: A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: International Business Machines CorporationInventors: Takashi Ando, Huiming Bu, Ramachandra Divakaruni, Bruce B. Doris, Chung-Hsun Lin, Huiling Shang, Tenko Yamashita
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Patent number: 8232599Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: GrantFiled: January 7, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Publication number: 20120187492Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: ApplicationFiled: March 21, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Patent number: 8154130Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.Type: GrantFiled: April 23, 2008Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Christophe Detavernier, Simon Gaudet, Christian Lavoie, Huiling Shang
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Publication number: 20110318897Abstract: Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiling Shang, Ying Li, Henry K. Utomo
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Patent number: 8080838Abstract: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.Type: GrantFiled: May 1, 2009Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Leland Chang, Wilfried E. Haensch, Meikei Ieong, Ghavam Shahidi, Huiling Shang
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Publication number: 20110163383Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: ApplicationFiled: January 7, 2010Publication date: July 7, 2011Applicant: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Publication number: 20100237425Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.Type: ApplicationFiled: March 19, 2010Publication date: September 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor W.C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan, Roger Allen Booth, JR.