Patents by Inventor Hung Chou

Hung Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085671
    Abstract: An annular light trapping component includes an inner surface, an outer surface, an object-side surface and an image-side surface. The inner surface includes multiple L-shaped annular grooves. The annular light trapping component includes multiple stripe-shaped structures in the L-shaped annular grooves. The L-shaped annular grooves include an object-side L-shaped annular groove closest to the object-side surface and an image-side L-shaped annular groove closest to the image-side surface. A bottom diameter of the image-side L-shaped annular groove is larger than a bottom diameter of the object-side L-shaped annular groove. Each L-shaped annular groove includes a first side and a second side located between the object-side surface and the image-side surface. The stripe-shaped structures are disposed on the first side or the second side. A degree of inclination between the first side and the central axis is larger than a degree of inclination between the second side and the central axis.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Ming-Ta CHOU, Cheng-Feng LIN, Wei-Hung WENG
  • Publication number: 20240089611
    Abstract: The present invention relates to a method of image fusion, which uses the brightness difference of the current frame and the previous frame to determine whether the pixel in a frame image is static or dynamic. If the current pixel is static, the previous corresponding pixel is superimposed onto the current pixel; if the current pixel is dynamic, the previous corresponding pixel is replaced with the current pixel.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 14, 2024
    Inventors: Ping-Hung Yin, Yung-Ming Chou, Bo-Jia Lin, Yu-Sheng Liao
  • Publication number: 20240087953
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 11925912
    Abstract: The disclosure features a system that includes a plurality of material tanks, each of which includes at least one material for forming a chemical composition and includes a first recirculation loop; at least one mixing tank in which the materials from the material tanks are mixed to form a chemical composition, the mixing tank including a second recirculation loop; and at least one holding tank configured to continuously receive the chemical composition from the mixing tank, the holding tank including a third recirculation loop. The system may further include a plurality of fluid flow controller units and be configured to form material and chemical composition flows in an in-process steady state.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 12, 2024
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Shih-Pin Chou, Wen-Hung Chang, Deepak Mahulikar, Tamas Varga, Abhudaya Mishra
  • Publication number: 20240079485
    Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 7, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jih-Wen Chou, Chih-Hung Lu, Bo-An Tsai, Zheng-Chang Mu, Po-Hsien Yeh, Robin Christine Hwang
  • Patent number: 11923425
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen, Chiu-Hua Chung
  • Patent number: 11914429
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Patent number: 11917436
    Abstract: A base station (BS) and a method for wireless communication are provided. The method includes transmitting a first radio resource control (RRC) configuration that configures a radio link monitoring configuration that includes a beam failure detection (BFD) timer and a beam failure indication (BFI) count threshold. The first RRC configuration enables a user equipment (UE) to: start or restart the BFD timer by a medium access control (MAC) entity of the UE each time a BFI is received from a lower layer; and initiate a beam failure recovery (BFR) procedure upon determining that the number of the received BFIs is greater than or equal to the BFI count threshold. The method further includes transmitting a second RRC configuration that reconfigures the radio link monitoring configuration. The second RRC configuration enables the UE to set the BFI counter to zero in response to receiving the second RRC configuration.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: February 27, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chia-Hung Wei, Chie-Ming Chou
  • Patent number: 11905299
    Abstract: The present disclosure relates generally to modulators of Cot (cancer Osaka thyroid) and methods of use and manufacture thereof.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: February 20, 2024
    Assignee: Gilead Sciences, Inc.
    Inventors: Elizabeth M. Bacon, Gayatri Balan, Chien-Hung Chou, Christopher T. Clark, Jeromy J. Cottell, Musong Kim, Thorsten A. Kirschberg, John O. Link, Gary Phillips, Scott D. Schroeder, Neil H. Squires, Kirk L. Stevens, James G. Taylor, William J. Watkins, Nathan E. Wright, Sheila M. Zipfel
  • Publication number: 20240055274
    Abstract: A semiconductor package carrier board structure includes a plurality of carrier board bodies and a plurality of supporting bumps. The carrier board body includes a build-up circuit structure and a plurality of conductive blocks bonded to the build-up circuit structure. Adjacent ones of the carrier board bodies are connected to each other with their corresponding conductive blocks. An area formed by the adjacent conductive blocks defines a cutting path. An opening is formed on a surface of each of the conductive blocks at the cutting path. The supporting bumps are erected between the adjacent openings. As such, each of the supporting bumps corresponds to a position overlapping the cutting path to provide the support function of the semiconductor package carrier board structure when performing the semiconductor packaging operation. After performing the singulation operation, the supporting bumps can be completely removed and one side of the openings can be exposed.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 15, 2024
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung CHOU, Ming-Yeh CHANG
  • Patent number: 11899188
    Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The first lens group includes a first lens and a second lens, and the second lens group includes a third lens and a fourth lens. One of the third lens and the fourth lens includes one aspheric surface, and each of the lenses in the optical lens system is a singlet lens. The optical lens satisfies a condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 13, 2024
    Assignee: YOUNG OPTICS INC.
    Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang
  • Publication number: 20240019150
    Abstract: An air purification device and a method of estimating air filter lifetime are disclosed. The method of estimating air filter lifetime includes steps of: detecting, by an air quality sensing module, an air quality of an airflow before the airflow is filtered by a filter module to generate an air quality sensing value correspondingly; calculating consumption values of the filter module according to the air quality sensing value by a computation module; continuously calculating and updating an estimated lifetime value of the filter module by using the consumption values based on a frequency by the computation module; and when the estimated lifetime value of the filter module is not greater than a threshold, generating a notification command of changing the filter module.
    Type: Application
    Filed: October 5, 2022
    Publication date: January 18, 2024
    Inventors: Wen-Faung HSU, Chia-Heng HSU, Hung-Chou CHEN
  • Patent number: 11870296
    Abstract: An uninterruptible power system and an operation method thereof are provided. The uninterruptible power system comprises a DC-AC conversion circuit, a plurality of switches, a plurality of sensing units, a plurality of output ports and a control unit. Each output port is electrically coupled to an output terminal of the DC-AC conversion circuit sequentially through one of the sensing units and one of the switches. The control unit is configured to define members of at least one group from the output ports according to a system setting, and define which members of each group are non-critical output ports according to the system setting. The control unit is further configured to set, according to the system setting, at least one condition for all non-critical output ports in each group to simultaneously stop supplying power, and to accordingly control the operations of the corresponding switches.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 9, 2024
    Assignee: CYBER POWER SYSTEMS, INC.
    Inventors: Kai-Tsung Yang, Jui-Hung Chou, Fang-Yu Hsu, Shou-Ting Yeh
  • Publication number: 20240000952
    Abstract: Disclosed herein are methods and kits for identifying responsiveness or non-responsiveness of a cancer subject to arginine deprivation therapy. The method includes determining the presence of a G/G genotype of rs13338697 of the target nucleic acid in a biological sample derived from the subject by use of a polymerase chain reaction (PCR)-based method, in which the presence of the G/G genotype of rs13338697 of the target nucleic acid is an indication that the subject is responsive to the arginine deprivation therapy.
    Type: Application
    Filed: April 14, 2022
    Publication date: January 4, 2024
    Inventors: Hung-Wen CHEN, Hui-Fen LIU, Chau-Ting YEH, Yu-De CHU, Chun-Hung CHOU
  • Patent number: 11862675
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20230395703
    Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hao LIN, Chia-Hung CHOU, Chih-Hsuan CHEN, Ping-En CHENG, Hsin-Wen SU, Chien-Chih LIN, Szu-Chi YANG
  • Publication number: 20230343816
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
  • Patent number: 11791281
    Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 17, 2023
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
  • Patent number: 11780877
    Abstract: The present invention provides a method of sugar-guided modifying a glycosylated polypeptide. First, a boronic acid group of a probe molecule and a sugar group of the glycosylated polypeptide form a first covalent bond. Next, an alkyne group of a modifying group and an azide group of the probe molecule form a second covalent bond by adding a promoter. As a result, the modifying group can be close to the glycosylated polypeptide. Then, the modifying group can bind to a nucleophilic residue that is near the sugar group, through a nucleophilic addition reaction. The method of the present invention can selectively modify a given site with the guidance of the sugar group.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: October 10, 2023
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Po-Chiao Lin, Chih-Hung Chou
  • Publication number: 20230291454
    Abstract: A method of channel state information (CSI) report can include receiving a CSI report configuration at a user equipment (UE) from a base station, the CSI report configuration being associated with a set of CSI reference signal (CSI-RS) resources corresponding to multiple transmission reception points (TRPs), performing a channel measurement based on the CSI-RSs resources corresponding to the multiple TRPs, determining a precoder matrix indicator (PMI) based on measurement results of the channel measurement, the PMI corresponding to a precoder matrix, denoted W, of a Type II CSI codebook, the precoder matrix having a spatial domain (SD) basis vector matrix, denoted W1, SD basis selection of the SD basis vector matrix being TRP-specific, and transmitting a CSI report to the base station, the CSI report including the PMI.
    Type: Application
    Filed: February 15, 2023
    Publication date: September 14, 2023
    Applicant: MEDIATEK INC.
    Inventors: Kuan-Hung CHOU, Chin-Kuo JAO, Sandeep BHAT