Abstract: A layout optimization method and a semiconductor wafer are provided. The method includes: generating adjusted patterns corresponding to a first layout pattern; generating a layout optimization test group according to the adjusted patterns, wherein the layout optimization test group includes first and second clusters of test pattern arrays, the first cluster include first test pattern arrays in accordance with one of the adjusted patterns and different from one another in terms of capacity, and the second cluster include second test pattern arrays in accordance with another one of the adjusted patterns and different from one another in terms of capacity; forming the layout optimization test group on a wafer; performing an electrical inspection on the first and second pattern arrays, and determining a best manufacturing solution from the adjusted patterns according to the electrical inspection.

Abstract: A cosmetic case includes a case bottom, an intermediate layer, and a lid. The case bottom is provided with a pivot slot and a guiding surface at a position corresponding to the pivot slot. The intermediate layer is detachably combined in the case bottom and provided with an abutting arm which abuts against the guiding surface of the case bottom. The lid is openably covered on the case bottom and includes a pivot block which is held in the pivot slot of the case bottom. When the lid is opened, the pivot block is in contact with the abutting arm of the intermediate layer, so that when the lid is pressed down, the abutting arm will move upward relative to the case bottom under the guidance of the guiding surface, and thus the intermediate layer can be easily disassembled from the case bottom.

Abstract: A sensor with plurality of sensor elements arranged on a flexible substrate, including a flexible substrate, multiple perforations formed in the flexible substrate, multiple open-ended moat-like cut-out areas formed in the flexible substrate, wherein the perforations and the open-ended moat-like cut-out areas are arranged in a staggered array on the flexible substrate, and each open-ended moat-like cut-out area defines an active area nearly enclosed by one open-ended moat-like cut-out area and connecting the flexible substrate through a bridge feature not enclosed by the open-ended moat-like cut-out area, and multiple sensor elements, wherein each sensor element is set on one active area.

Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.

Abstract: A laser colored product, a laser coloring method therefor, and a laser coloring system using the same are provided. The laser coloring method comprises the following steps. First, provide a processing workpiece which includes a processing part, and the processing part includes a pattern region. The processing part within the pattern region includes an inner portion and an outer layer, and the outer layer includes metal materials. Use the laser coloring system to irradiate the outer layer of the pattern region in stages to convert the outer layer of the pattern region into a metal color pattern layer. The metal color pattern layer includes metal materials or metal compounds of metal materials, and the metal color pattern layer includes a plurality of pixel units arranged in arrays, wherein each of the pixel units includes a pixel color, and each of the pixel units has a pixel width or a pixel length between 1 ?m to 500 ?m.

Abstract: A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack.

Abstract: Systems for unlocking and locking a riser cage to a computing device are described herein. Such systems may include: a riser cage in a computing device; an axis member coupled to a first side of the riser cage and adapted to rotate about an axis; a handle coupled to the axis member and adapted to rotate the axis member about the axis; a cam, coupled to the axis member, and adapted to rotate about the axis when the axis member rotates; and a lever coupled to a second side of the riser cage and adapted to rotate about a pivot point when the cam rotates, wherein the lever engages with a stabilizing feature when the handle is in a first handle position.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: An information handling system may include a backplane configured to couple at a first side thereof to a plurality of physical storage resources, an air mover configured to provide cooling to the information handling system, and a shelf coupled to the backplane at a second, opposite side thereof, wherein the shelf is disposed between the first side of the backplane and the air mover. The shelf may include an acoustically absorbent material.

Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a first doped well doped with a first impurity having a first conductivity type, a second doped well adjacent the first doped well and doped with a second impurity having a second conductivity type opposite the first conductivity type, a third doped well adjacent the second doped well and doped with a third impurity having the first conductivity type, a fourth doped region in the third doped well and doped with a fourth impurity having the second conductivity type, and a deep doped well doped with a fifth impurity having the first conductivity type under a first portion of the second doped well, under the third doped well, and under the fourth doped region.

Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.

Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: The present disclosure relates generally to modulators of Cot (cancer Osaka thyroid) and methods of use and manufacture thereof.

Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.

Abstract: An inductor structure is provided, in which a coil-shaped inductor body and a magnetically permeable alloy layer located in the coil are embedded in an insulator, so as to improve the electrical characteristics of the inductor via the design of the magnetically permeable alloy layer. Therefore, the inductor structure of the present disclosure can meet the required requirements without using a mixture of conventional magnetically permeable elements and conventional magnetic powders.

Abstract: A package carrier board includes a first circuit build-up structure, a patterned magnetic conductive metal layer, a plurality of first conductive pillar, a second insulating layer, and a second circuit build-up structure. The patterned magnetic conductive metal layer is disposed above the first circuit build-up structure, and the cross-sectional pattern of the patterned magnetic conductive metal layer is L-shaped and/or U-shaped. The first conductive pillars are disposed on the first circuit build-up structure and located outside of the patterned magnetic conductive metal layer. The second insulating layer covers the patterned magnetic conductive metal layer and the first conductive pillars. The second circuit build-up structure is disposed on the second insulating layer. The first circuit build-up structure, the first conductive pillars, the second insulating layer, and the second circuit build-up structure are combined to form an inductive circuit structure.

Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: An inductor structure is provided, in which an inductance coil in the shape of a toroidal coil or a helical coil is arranged in an insulator, and a magnetically permeable body made of a magnetically permeable material is a multi-layer stacked structure and arranged in the inductance coil, where the magnetically permeable body is free from being electrically connected to the inductance coil. Therefore, the magnetically permeable body made of a magnetically permeable material in the form of a multi-layer stacked structure may effectively improve the electrical characteristics of the inductor structure.