Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: Embodiments can provide a computer implemented method in a data processing system comprising a processor and a memory comprising instructions, which are executed by the processor to cause the processor to implement a system for network protection, the method comprising determining, by the processor, if an incoming connection comprising one or more packets has a false latency larger than a trigger latency; determining, by the processor, if an attack is currently in progress; and if the attack is in progress, injecting, by the processor, at least one of the one or more packets of the incoming connection or one or more packets of an outgoing connection with a false latency.

Abstract: A semiconductor package structure includes a substrate. The substrate includes a first ground layer. The first ground layer has a body and a first tooth protruding from a side of the body. The first tooth has a first lateral side. The first lateral side of the first tooth is inclined relative to the side of the body in a top view of the first ground layer.

Abstract: A control arm assembly mechanism includes: a workbench having thereon a holder; a vertically pressing device disposed above the workbench and including a moving arm capable of moving toward and away from the holder; and two transversely pressing devices flanking the workbench and each including a moving arm capable of moving toward and away from the holder. The control arm assembly mechanism operates in such a manner to compress transversely and vertically a bushing placed on the workbench and thereby fit the bushing into a control arm.

Abstract: A heat exchange system includes a heat-absorbing substance such as Liquid Natural Gas (LNG), a heat dissipation apparatus, a water storage tank, a heating portion, and a cooling portion. The heating portion is coupled between the LNG and the water storage tank. The cooling portion is coupled between the heat dissipation apparatus and the water storage tank. The cooling portion transfers heat of the heat dissipation apparatus to water of the water storage tank to heat the heating portion, and the heating portion transfers heat of the water of the water storage tank to the LNG.

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: A projection lens structure mainly includes a first group of lenses with a negative dioptric value, a second group of lenses with a positive dioptric value, a third group of lenses with a positive dioptric value and a fourth group of lenses with a negative dioptric value. The first group of lenses further includes at least a first lens and a second lens, of which the first lens ha a plastic aspheric lens in a meniscus shape with a focal length between ?25˜?80 mm. The second group of lenses further includes at least a third lens. The third group of lenses further includes at least a first doublet with a focal length between 25˜80 mm. The fourth group of length further includes at least a group of doublets, a fourth lens and a fifth lens.

Abstract: The present disclosure relates generally to modulators of Cot (cancer Osaka thyroid) and methods of use and manufacture thereof.

Abstract: A method for fabricating an interposer substrate is provided, including forming a wiring layer on a carrier, forming an insulating layer on the carrier, forming on the wiring layer a wiring build-up layer structure that is electrically connected to the wiring layer, forming on the wiring build-up layer structure external connection pillars that are electrically connected to the wiring build-up layer structure, and removing the carrier, with the wiring layer is exposed from a surface of the insulating layer. The fabrication process of the via can be bypassed in the fabrication process by forming coreless interposer substrate on the carrier, such that the overall cost of the fabrication process can be decreased, and the fabrication process is simple. This invention further provides the interposer substrate.

Abstract: A method for establishing a link for a keyword within a page or document being currently displayed includes detecting at least one keyword in the current display of the electronic device, and uploading the at least one keyword to a server. The method further includes receiving a link of relevant data of each keyword from the server, and displaying the link of the relevant data corresponding to each keyword in the currently displayed page of the display screen.

Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

Abstract: Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.

Abstract: An off-line uninterruptible power system and two line-interactive uninterruptible power systems are provided. The off-line uninterruptible power system and one of the line-interactive uninterruptible power systems additionally adopt a transformer for supplying an AC output, with lower voltage level than a rated output voltage, to at least one electrical device (especially those with resistive load characteristic). The other line-interactive uninterruptible power system controls its automatic voltage regulating circuit to supply an AC output, with lower voltage level than a rated output voltage, to at least one electrical device (especially those with resistive load characteristic).

Abstract: The invention provides compounds of formula (I): or a salt thereof as described herein. The invention also provides pharmaceutical compositions comprising a compound of formula (I), processes for preparing compounds of formula (I), intermediates useful for preparing compounds of formula I and therapeutic methods for treating a Retroviridae viral infection including an infection caused by the HIV virus.

Abstract: A power supplying device comprising a battery, a charging circuit and a DC-AC conversion circuit is provided. The charging circuit is electrically coupled to an AC power source and configured to charge the battery. The DC-AC conversion circuit is electrically coupled to the battery and configured to supply an AC output. When the power supplying device is powered on, both of the charging circuit and the DC-AC conversion circuit are enabled.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: Pesticidal compositions for improving physical characteristics of pesticide formulations which comprise natural pesticidal oil active ingredients are disclosed. One such composition comprises a pesticidal natural oil active ingredient, a surfactant to disperse the active ingredient in a water emulsion and a polymeric pour point depressant effective to reduce a pour point temperature of the pesticidal natural oil active ingredient. Methods for providing pesticidal compositions and application to control one or more pests are also disclosed.

Abstract: A method for downlink transmission in a cloud radio access network for a number of users is applied in a central unit. The central unit determines a specific number of remote radio heads (RRHs) as non-serving RRHs based on a predetermined data compression ratio. For each of many pieces of user equipment (UEs), the central unit determines a combination of RRHs which are non-serving in coordinated multi-point transmission (CoMP) from a plurality of RRHs based on the determined specific number, and then performs CoMP downlink transmission based on the combination of RRHs which are non-serving in the CoMP.